diff options
| author | Schuyler Eldridge | 2019-09-16 19:03:37 -0400 |
|---|---|---|
| committer | GitHub | 2019-09-16 19:03:37 -0400 |
| commit | f93e1d240f80848dc12c25906239fe6c8a4d42b5 (patch) | |
| tree | 9b39634fc4bd5044e37939a0bd568ae4ed158826 /src | |
| parent | 7e39ea8ec948ff1db7ccd0d850923a86d2d8a4e7 (diff) | |
| parent | b3dd7924f27342083681be6dd5932ef95d354029 (diff) | |
Merge pull request #1124 from freechipsproject/gender-to-flow
Gender to Flow
Diffstat (limited to 'src')
46 files changed, 459 insertions, 366 deletions
diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala index 854e1876..d7c73e39 100644 --- a/src/main/scala/firrtl/Emitter.scala +++ b/src/main/scala/firrtl/Emitter.scala @@ -189,11 +189,11 @@ class VerilogEmitter extends SeqTransform with Emitter { else if (e2 == we(one)) e1.e1 else DoPrim(And, Seq(e1.e1, e2.e1), Nil, UIntType(IntWidth(1))) } - def wref(n: String, t: Type) = WRef(n, t, ExpKind, UNKNOWNGENDER) + def wref(n: String, t: Type) = WRef(n, t, ExpKind, UnknownFlow) def remove_root(ex: Expression): Expression = ex match { case ex: WSubField => ex.expr match { case (e: WSubField) => remove_root(e) - case (_: WRef) => WRef(ex.name, ex.tpe, InstanceKind, UNKNOWNGENDER) + case (_: WRef) => WRef(ex.name, ex.tpe, InstanceKind, UnknownFlow) } case _ => throwInternalError(s"shouldn't be here: remove_root($ex)") } @@ -466,7 +466,7 @@ class VerilogEmitter extends SeqTransform with Emitter { case sx: Connect => netlist(sx.loc) = sx.expr case sx: IsInvalid => error("Should have removed these!") case sx: DefNode => - val e = WRef(sx.name, sx.value.tpe, NodeKind, MALE) + val e = WRef(sx.name, sx.value.tpe, NodeKind, SourceFlow) netlist(e) = sx.value case _ => } @@ -614,7 +614,7 @@ class VerilogEmitter extends SeqTransform with Emitter { val rstring = rand_string(s.dataType) initials += Seq("`ifdef RANDOMIZE_MEM_INIT") initials += Seq("for (initvar = 0; initvar < ", bigIntToVLit(s.depth), "; initvar = initvar+1)") - initials += Seq(tab, WSubAccess(wref(s.name, s.dataType), index, s.dataType, FEMALE), + initials += Seq(tab, WSubAccess(wref(s.name, s.dataType), index, s.dataType, SinkFlow), " = ", rstring, ";") initials += Seq("`endif // RANDOMIZE_MEM_INIT") } @@ -725,7 +725,7 @@ class VerilogEmitter extends SeqTransform with Emitter { initialize(e, sx.reset, sx.init) case sx: DefNode => declare("wire", sx.name, sx.value.tpe, sx.info) - assign(WRef(sx.name, sx.value.tpe, NodeKind, MALE), sx.value, sx.info) + assign(WRef(sx.name, sx.value.tpe, NodeKind, SourceFlow), sx.value, sx.info) case sx: Stop => simulate(sx.clk, sx.en, stop(sx.ret), Some("STOP_COND"), sx.info) case sx: Print => @@ -781,8 +781,8 @@ class VerilogEmitter extends SeqTransform with Emitter { //; Read port assign(addr, netlist(addr), NoInfo) // Info should come from addr connection // assign(en, netlist(en)) //;Connects value to m.r.en - val mem = WRef(sx.name, memType(sx), MemKind, UNKNOWNGENDER) - val memPort = WSubAccess(mem, addr, sx.dataType, UNKNOWNGENDER) + val mem = WRef(sx.name, memType(sx), MemKind, UnknownFlow) + val memPort = WSubAccess(mem, addr, sx.dataType, UnknownFlow) val depthValue = UIntLiteral(sx.depth, IntWidth(sx.depth.bitLength)) val garbageGuard = DoPrim(Geq, Seq(addr, depthValue), Seq(), UnknownType) @@ -812,8 +812,8 @@ class VerilogEmitter extends SeqTransform with Emitter { assign(mask, netlist(mask), NoInfo) assign(en, netlist(en), NoInfo) - val mem = WRef(sx.name, memType(sx), MemKind, UNKNOWNGENDER) - val memPort = WSubAccess(mem, addr, sx.dataType, UNKNOWNGENDER) + val mem = WRef(sx.name, memType(sx), MemKind, UnknownFlow) + val memPort = WSubAccess(mem, addr, sx.dataType, UnknownFlow) update(memPort, data, clk, AND(en, mask), sx.info) } diff --git a/src/main/scala/firrtl/LoweringCompilers.scala b/src/main/scala/firrtl/LoweringCompilers.scala index 274ccf74..05cdbe96 100644 --- a/src/main/scala/firrtl/LoweringCompilers.scala +++ b/src/main/scala/firrtl/LoweringCompilers.scala @@ -29,7 +29,7 @@ class IRToWorkingIR extends CoreTransform { def transforms = Seq(passes.ToWorkingIR) } -/** Resolves types, kinds, and genders, and checks the circuit legality. +/** Resolves types, kinds, and flows, and checks the circuit legality. * Operates on working IR nodes and high Firrtl. */ class ResolveAndCheck extends CoreTransform { @@ -43,8 +43,8 @@ class ResolveAndCheck extends CoreTransform { passes.Uniquify, passes.ResolveKinds, passes.InferTypes, - passes.ResolveGenders, - passes.CheckGenders, + passes.ResolveFlows, + passes.CheckFlows, new passes.InferWidths, passes.CheckWidths, new firrtl.transforms.InferResets) @@ -70,7 +70,7 @@ class HighFirrtlToMiddleFirrtl extends CoreTransform { passes.InferTypes, passes.CheckTypes, new checks.CheckResets, - passes.ResolveGenders, + passes.ResolveFlows, new passes.InferWidths, passes.CheckWidths, passes.ConvertFixedToSInt, @@ -89,7 +89,7 @@ class MiddleFirrtlToLowFirrtl extends CoreTransform { passes.LowerTypes, passes.ResolveKinds, passes.InferTypes, - passes.ResolveGenders, + passes.ResolveFlows, new passes.InferWidths, passes.Legalize, new firrtl.transforms.RemoveReset, diff --git a/src/main/scala/firrtl/Utils.scala b/src/main/scala/firrtl/Utils.scala index 91da600a..4bf2d14d 100644 --- a/src/main/scala/firrtl/Utils.scala +++ b/src/main/scala/firrtl/Utils.scala @@ -34,9 +34,9 @@ object toBits { } private def hiercat(e: Expression): Expression = e.tpe match { case t: VectorType => seqCat((0 until t.size).reverse map (i => - hiercat(WSubIndex(e, i, t.tpe, UNKNOWNGENDER)))) + hiercat(WSubIndex(e, i, t.tpe, UnknownFlow)))) case t: BundleType => seqCat(t.fields map (f => - hiercat(WSubField(e, f.name, f.tpe, UNKNOWNGENDER)))) + hiercat(WSubField(e, f.name, f.tpe, UnknownFlow)))) case t: GroundType => DoPrim(AsUInt, Seq(e), Seq.empty, UnknownType) case t => Utils.error(s"Unknown type encountered in toBits: $e") } @@ -63,18 +63,18 @@ object bitWidth { object castRhs { def apply(lhst: Type, rhs: Expression) = { (lhst, rhs.tpe) match { - case (x: GroundType, y: GroundType) if WrappedType(x) == WrappedType(y) => + case (x: GroundType, y: GroundType) if WrappedType(x) == WrappedType(y) => rhs - case (_: SIntType, _) => + case (_: SIntType, _) => DoPrim(AsSInt, Seq(rhs), Seq.empty, lhst) - case (FixedType(_, IntWidth(p)), _) => + case (FixedType(_, IntWidth(p)), _) => DoPrim(AsFixedPoint, Seq(rhs), Seq(p), lhst) - case (ClockType, _) => + case (ClockType, _) => DoPrim(AsClock, Seq(rhs), Seq.empty, lhst) - case (_: UIntType, _) => + case (_: UIntType, _) => DoPrim(AsUInt, Seq(rhs), Seq.empty, lhst) case (_, _) => Utils.error("castRhs lhst, rhs type combination is invalid") - } + } } } @@ -102,13 +102,13 @@ object fromBits { lhst match { case t: VectorType => (0 until t.size foldLeft( (offset, Seq[Statement]()) )) { case ((curOffset, stmts), i) => - val subidx = WSubIndex(lhs, i, t.tpe, UNKNOWNGENDER) + val subidx = WSubIndex(lhs, i, t.tpe, UnknownFlow) val (tmpOffset, substmts) = getPart(subidx, t.tpe, rhs, curOffset) (tmpOffset, stmts ++ substmts) } case t: BundleType => (t.fields foldRight( (offset, Seq[Statement]()) )) { case (f, (curOffset, stmts)) => - val subfield = WSubField(lhs, f.name, f.tpe, UNKNOWNGENDER) + val subfield = WSubField(lhs, f.name, f.tpe, UnknownFlow) val (tmpOffset, substmts) = getPart(subfield, f.tpe, rhs, curOffset) (tmpOffset, stmts ++ substmts) } @@ -228,7 +228,7 @@ object Utils extends LazyLogging { val zero = UIntLiteral(0) def create_exps(n: String, t: Type): Seq[Expression] = - create_exps(WRef(n, t, ExpKind, UNKNOWNGENDER)) + create_exps(WRef(n, t, ExpKind, UnknownFlow)) def create_exps(e: Expression): Seq[Expression] = e match { case ex: Mux => val e1s = create_exps(ex.tval) @@ -240,8 +240,8 @@ object Utils extends LazyLogging { case ex => ex.tpe match { case (_: GroundType) => Seq(ex) case t: BundleType => - t.fields.flatMap(f => create_exps(WSubField(ex, f.name, f.tpe,times(gender(ex), f.flip)))) - case t: VectorType => (0 until t.size).flatMap(i => create_exps(WSubIndex(ex, i, t.tpe,gender(ex)))) + t.fields.flatMap(f => create_exps(WSubField(ex, f.name, f.tpe,times(flow(ex), f.flip)))) + case t: VectorType => (0 until t.size).flatMap(i => create_exps(WSubIndex(ex, i, t.tpe,flow(ex)))) } } @@ -260,9 +260,9 @@ object Utils extends LazyLogging { case ex => ex.tpe match { case (_: GroundType) => Seq(ex) case (t: BundleType) => (t.fields foldLeft Seq[Expression](ex))((exps, f) => - exps ++ create_exps(WSubField(ex, f.name, f.tpe,times(gender(ex), f.flip)))) + exps ++ create_exps(WSubField(ex, f.name, f.tpe,times(flow(ex), f.flip)))) case (t: VectorType) => (0 until t.size foldLeft Seq[Expression](ex))((exps, i) => - exps ++ create_exps(WSubIndex(ex, i, t.tpe,gender(ex)))) + exps ++ create_exps(WSubIndex(ex, i, t.tpe,flow(ex)))) } } def toTarget(main: String, module: String)(expression: Expression): ReferenceTarget = { @@ -283,7 +283,7 @@ object Utils extends LazyLogging { onExp(expression) ReferenceTarget(main, module, Nil, ref, tokens) } - @deprecated("get_flip is fundamentally slow, use to_flip(gender(expr))", "1.2") + @deprecated("get_flip is fundamentally slow, use to_flip(flow(expr))", "1.2") def get_flip(t: Type, i: Int, f: Orientation): Orientation = { if (i >= get_size(t)) throwInternalError(s"get_flip: shouldn't be here - $i >= get_size($t)") t match { @@ -308,7 +308,7 @@ object Utils extends LazyLogging { flip.get } } - + def get_point (e:Expression) : Int = e match { case (e: WRef) => 0 case (e: WSubField) => e.expr.tpe match {case b: BundleType => @@ -418,7 +418,7 @@ object Utils extends LazyLogging { } case vx => UnknownType } - + // ================================= def error(str: String, cause: Throwable = null) = throw new FirrtlInternalException(str, cause) @@ -473,12 +473,12 @@ object Utils extends LazyLogging { } } -// =========== GENDER/FLIP UTILS ============ - def swap(g: Gender) : Gender = g match { - case UNKNOWNGENDER => UNKNOWNGENDER - case MALE => FEMALE - case FEMALE => MALE - case BIGENDER => BIGENDER +// =========== FLOW/FLIP UTILS ============ + def swap(g: Flow) : Flow = g match { + case UnknownFlow => UnknownFlow + case SourceFlow => SinkFlow + case SinkFlow => SourceFlow + case DuplexFlow => DuplexFlow } def swap(d: Direction) : Direction = d match { case Output => Input @@ -488,21 +488,26 @@ object Utils extends LazyLogging { case Default => Flip case Flip => Default } - def to_dir(g: Gender): Direction = g match { - case MALE => Input - case FEMALE => Output + def to_dir(g: Flow): Direction = g match { + case SourceFlow => Input + case SinkFlow => Output } + @deprecated("Migrate from 'Gender' to 'Flow. This method will be removed in 1.3", "1.2") def to_gender(d: Direction): Gender = d match { case Input => MALE case Output => FEMALE } + def to_flow(d: Direction): Flow = d match { + case Input => SourceFlow + case Output => SinkFlow + } def to_flip(d: Direction): Orientation = d match { case Input => Flip case Output => Default } - def to_flip(g: Gender): Orientation = g match { - case MALE => Flip - case FEMALE => Default + def to_flip(g: Flow): Orientation = g match { + case SourceFlow => Flip + case SinkFlow => Default } def field_flip(v: Type, s: String): Orientation = v match { @@ -524,14 +529,14 @@ object Utils extends LazyLogging { case Default => d case Flip => swap(d) } - def times(g: Gender, d: Direction): Direction = times(d, g) - def times(d: Direction, g: Gender): Direction = g match { - case FEMALE => d - case MALE => swap(d) // MALE == INPUT == REVERSE + def times(g: Flow, d: Direction): Direction = times(d, g) + def times(d: Direction, g: Flow): Direction = g match { + case SinkFlow => d + case SourceFlow => swap(d) // SourceFlow == INPUT == REVERSE } - def times(g: Gender, flip: Orientation): Gender = times(flip, g) - def times(flip: Orientation, g: Gender): Gender = flip match { + def times(g: Flow, flip: Orientation): Flow = times(flip, g) + def times(flip: Orientation, g: Flow): Flow = flip match { case Default => g case Flip => swap(g) } @@ -548,6 +553,7 @@ object Utils extends LazyLogging { case ex: WSubAccess => kind(ex.expr) case ex => ExpKind } + @deprecated("Migrate from 'Gender' to 'Flow'. This method will be removed in 1.3", "1.2") def gender(e: Expression): Gender = e match { case ex: WRef => ex.gender case ex: WSubField => ex.gender @@ -561,6 +567,7 @@ object Utils extends LazyLogging { case WInvalid => MALE case ex => throwInternalError(s"gender: shouldn't be here - $e") } + @deprecated("Migrate from 'Gender' to 'Flow'. This method will be removed in 1.3", "1.2") def get_gender(s: Statement): Gender = s match { case sx: DefWire => BIGENDER case sx: DefRegister => BIGENDER @@ -576,7 +583,37 @@ object Utils extends LazyLogging { case sx: IsInvalid => UNKNOWNGENDER case EmptyStmt => UNKNOWNGENDER } + @deprecated("Migrate from 'Gender' to 'Flow'. This method will be removed in 1.3", "1.2") def get_gender(p: Port): Gender = if (p.direction == Input) MALE else FEMALE + def flow(e: Expression): Flow = e match { + case ex: WRef => ex.flow + case ex: WSubField => ex.flow + case ex: WSubIndex => ex.flow + case ex: WSubAccess => ex.flow + case ex: DoPrim => SourceFlow + case ex: UIntLiteral => SourceFlow + case ex: SIntLiteral => SourceFlow + case ex: Mux => SourceFlow + case ex: ValidIf => SourceFlow + case WInvalid => SourceFlow + case ex => throwInternalError(s"flow: shouldn't be here - $e") + } + def get_flow(s: Statement): Flow = s match { + case sx: DefWire => DuplexFlow + case sx: DefRegister => DuplexFlow + case sx: WDefInstance => SourceFlow + case sx: DefNode => SourceFlow + case sx: DefInstance => SourceFlow + case sx: DefMemory => SourceFlow + case sx: Block => UnknownFlow + case sx: Connect => UnknownFlow + case sx: PartialConnect => UnknownFlow + case sx: Stop => UnknownFlow + case sx: Print => UnknownFlow + case sx: IsInvalid => UnknownFlow + case EmptyStmt => UnknownFlow + } + def get_flow(p: Port): Flow = if (p.direction == Input) SourceFlow else SinkFlow def get_info(s: Statement): Info = s match { case s: HasInfo => s.info case _ => NoInfo @@ -598,23 +635,23 @@ object Utils extends LazyLogging { case e: WRef => (e, EmptyExpression) case e: WSubIndex => val (root, tail) = splitRef(e.expr) - (root, WSubIndex(tail, e.value, e.tpe, e.gender)) + (root, WSubIndex(tail, e.value, e.tpe, e.flow)) case e: WSubField => val (root, tail) = splitRef(e.expr) tail match { - case EmptyExpression => (root, WRef(e.name, e.tpe, root.kind, e.gender)) - case exp => (root, WSubField(tail, e.name, e.tpe, e.gender)) + case EmptyExpression => (root, WRef(e.name, e.tpe, root.kind, e.flow)) + case exp => (root, WSubField(tail, e.name, e.tpe, e.flow)) } } /** Adds a root reference to some SubField/SubIndex chain */ def mergeRef(root: Expression, body: Expression): Expression = body match { case e: WRef => - WSubField(root, e.name, e.tpe, e.gender) + WSubField(root, e.name, e.tpe, e.flow) case e: WSubIndex => - WSubIndex(mergeRef(root, e.expr), e.value, e.tpe, e.gender) + WSubIndex(mergeRef(root, e.expr), e.value, e.tpe, e.flow) case e: WSubField => - WSubField(mergeRef(root, e.expr), e.name, e.tpe, e.gender) + WSubField(mergeRef(root, e.expr), e.name, e.tpe, e.flow) case EmptyExpression => root } diff --git a/src/main/scala/firrtl/WIR.scala b/src/main/scala/firrtl/WIR.scala index c1839a22..73a20d18 100644 --- a/src/main/scala/firrtl/WIR.scala +++ b/src/main/scala/firrtl/WIR.scala @@ -20,13 +20,24 @@ case object MemKind extends Kind case object ExpKind extends Kind case object UnknownKind extends Kind -trait Gender -case object MALE extends Gender -case object FEMALE extends Gender -case object BIGENDER extends Gender -case object UNKNOWNGENDER extends Gender +trait Flow +case object SourceFlow extends Flow +case object SinkFlow extends Flow +case object DuplexFlow extends Flow +case object UnknownFlow extends Flow -case class WRef(name: String, tpe: Type, kind: Kind, gender: Gender) extends Expression { +private[firrtl] trait GenderFromFlow { this: Expression => + val flow: Flow + @deprecated("Migrate from 'Gender' to 'Flow'. This method will be removed in 1.3.", "1.2") + def gender: Gender = flow match { + case SourceFlow => MALE + case SinkFlow => FEMALE + case DuplexFlow => BIGENDER + case UnknownFlow => UNKNOWNGENDER + } +} + +case class WRef(name: String, tpe: Type, kind: Kind, flow: Flow) extends Expression with GenderFromFlow { def serialize: String = name def mapExpr(f: Expression => Expression): Expression = this def mapType(f: Type => Type): Expression = this.copy(tpe = f(tpe)) @@ -37,21 +48,21 @@ case class WRef(name: String, tpe: Type, kind: Kind, gender: Gender) extends Exp } object WRef { /** Creates a WRef from a Wire */ - def apply(wire: DefWire): WRef = new WRef(wire.name, wire.tpe, WireKind, UNKNOWNGENDER) + def apply(wire: DefWire): WRef = new WRef(wire.name, wire.tpe, WireKind, UnknownFlow) /** Creates a WRef from a Register */ - def apply(reg: DefRegister): WRef = new WRef(reg.name, reg.tpe, RegKind, UNKNOWNGENDER) + def apply(reg: DefRegister): WRef = new WRef(reg.name, reg.tpe, RegKind, UnknownFlow) /** Creates a WRef from a Node */ - def apply(node: DefNode): WRef = new WRef(node.name, node.value.tpe, NodeKind, MALE) + def apply(node: DefNode): WRef = new WRef(node.name, node.value.tpe, NodeKind, SourceFlow) /** Creates a WRef from a Port */ - def apply(port: Port): WRef = new WRef(port.name, port.tpe, PortKind, UNKNOWNGENDER) + def apply(port: Port): WRef = new WRef(port.name, port.tpe, PortKind, UnknownFlow) /** Creates a WRef from a WDefInstance */ - def apply(wi: WDefInstance): WRef = new WRef(wi.name, wi.tpe, InstanceKind, UNKNOWNGENDER) + def apply(wi: WDefInstance): WRef = new WRef(wi.name, wi.tpe, InstanceKind, UnknownFlow) /** Creates a WRef from a DefMemory */ - def apply(mem: DefMemory): WRef = new WRef(mem.name, passes.MemPortUtils.memType(mem), MemKind, UNKNOWNGENDER) + def apply(mem: DefMemory): WRef = new WRef(mem.name, passes.MemPortUtils.memType(mem), MemKind, UnknownFlow) /** Creates a WRef from an arbitrary string name */ - def apply(n: String, t: Type = UnknownType, k: Kind = ExpKind): WRef = new WRef(n, t, k, UNKNOWNGENDER) + def apply(n: String, t: Type = UnknownType, k: Kind = ExpKind): WRef = new WRef(n, t, k, UnknownFlow) } -case class WSubField(expr: Expression, name: String, tpe: Type, gender: Gender) extends Expression { +case class WSubField(expr: Expression, name: String, tpe: Type, flow: Flow) extends Expression with GenderFromFlow { def serialize: String = s"${expr.serialize}.$name" def mapExpr(f: Expression => Expression): Expression = this.copy(expr = f(expr)) def mapType(f: Type => Type): Expression = this.copy(tpe = f(tpe)) @@ -61,10 +72,10 @@ case class WSubField(expr: Expression, name: String, tpe: Type, gender: Gender) def foreachWidth(f: Width => Unit): Unit = Unit } object WSubField { - def apply(expr: Expression, n: String): WSubField = new WSubField(expr, n, field_type(expr.tpe, n), UNKNOWNGENDER) - def apply(expr: Expression, name: String, tpe: Type): WSubField = new WSubField(expr, name, tpe, UNKNOWNGENDER) + def apply(expr: Expression, n: String): WSubField = new WSubField(expr, n, field_type(expr.tpe, n), UnknownFlow) + def apply(expr: Expression, name: String, tpe: Type): WSubField = new WSubField(expr, name, tpe, UnknownFlow) } -case class WSubIndex(expr: Expression, value: Int, tpe: Type, gender: Gender) extends Expression { +case class WSubIndex(expr: Expression, value: Int, tpe: Type, flow: Flow) extends Expression with GenderFromFlow { def serialize: String = s"${expr.serialize}[$value]" def mapExpr(f: Expression => Expression): Expression = this.copy(expr = f(expr)) def mapType(f: Type => Type): Expression = this.copy(tpe = f(tpe)) @@ -73,7 +84,7 @@ case class WSubIndex(expr: Expression, value: Int, tpe: Type, gender: Gender) ex def foreachType(f: Type => Unit): Unit = f(tpe) def foreachWidth(f: Width => Unit): Unit = Unit } -case class WSubAccess(expr: Expression, index: Expression, tpe: Type, gender: Gender) extends Expression { +case class WSubAccess(expr: Expression, index: Expression, tpe: Type, flow: Flow) extends Expression with GenderFromFlow { def serialize: String = s"${expr.serialize}[${index.serialize}]" def mapExpr(f: Expression => Expression): Expression = this.copy(expr = f(expr), index = f(index)) def mapType(f: Type => Type): Expression = this.copy(tpe = f(tpe)) @@ -264,7 +275,7 @@ class WrappedType(val t: Type) { object WrappedWidth { def eqw(w1: Width, w2: Width): Boolean = new WrappedWidth(w1) == new WrappedWidth(w2) } - + class WrappedWidth (val w: Width) { def ww(w: Width): WrappedWidth = new WrappedWidth(w) override def toString = w match { @@ -285,10 +296,10 @@ class WrappedWidth (val w: Width) { case (w1: MinWidth, w2: MinWidth) => w1.args.size == w2.args.size && (w1.args forall (a1 => w2.args exists (a2 => eqw(a1, a2)))) case (w1: IntWidth, w2: IntWidth) => w1.width == w2.width - case (w1: PlusWidth, w2: PlusWidth) => + case (w1: PlusWidth, w2: PlusWidth) => (ww(w1.arg1) == ww(w2.arg1) && ww(w1.arg2) == ww(w2.arg2)) || (ww(w1.arg1) == ww(w2.arg2) && ww(w1.arg2) == ww(w2.arg1)) - case (w1: MinusWidth,w2: MinusWidth) => + case (w1: MinusWidth,w2: MinusWidth) => (ww(w1.arg1) == ww(w2.arg1) && ww(w1.arg2) == ww(w2.arg2)) || (ww(w1.arg1) == ww(w2.arg2) && ww(w1.arg2) == ww(w2.arg1)) case (w1: ExpWidth, w2: ExpWidth) => ww(w1.arg1) == ww(w2.arg1) @@ -365,4 +376,3 @@ case class CDefMPort(info: Info, def foreachString(f: String => Unit): Unit = f(name) def foreachInfo(f: Info => Unit): Unit = f(info) } - diff --git a/src/main/scala/firrtl/package.scala b/src/main/scala/firrtl/package.scala index eb68aef4..1e871c46 100644 --- a/src/main/scala/firrtl/package.scala +++ b/src/main/scala/firrtl/package.scala @@ -12,4 +12,27 @@ package object firrtl { @deprecated("Use firrtl.stage.TargetDirAnnotation", "1.2") val TargetDirAnnotation = firrtl.options.TargetDirAnnotation + + @deprecated("Use Flow instead of Gender. This trait will be removed in 1.3", "1.2") + trait Gender + + @deprecated("Use SourceFlow instead of MALE. This case object will be removed in 1.3", "1.2") + case object MALE extends Gender + + @deprecated("Use SinkFlow instead of FEMALE. This case object will be removed in 1.3", "1.2") + case object FEMALE extends Gender + + @deprecated("Use DuplexFlow instead of BIGENDER. This case object will be removed in 1.3", "1.2") + case object BIGENDER extends Gender + + @deprecated("Use UnknownFlow instead of UNKNOWNGENDER. This case object will be removed in 1.3", "1.2") + case object UNKNOWNGENDER extends Gender + + @deprecated("Please migrate from 'Gender' to 'Flow'. This implicit conversion will be removed in 1.3", "1.2") + implicit def genderToFlow(gender: Gender): Flow = gender match { + case MALE => SourceFlow + case FEMALE => SinkFlow + case BIGENDER => DuplexFlow + case UNKNOWNGENDER => UnknownFlow + } } diff --git a/src/main/scala/firrtl/passes/CheckInitialization.scala b/src/main/scala/firrtl/passes/CheckInitialization.scala index d1b6a03f..9fbf3eeb 100644 --- a/src/main/scala/firrtl/passes/CheckInitialization.scala +++ b/src/main/scala/firrtl/passes/CheckInitialization.scala @@ -18,14 +18,14 @@ object CheckInitialization extends Pass { private case class VoidExpr(stmt: Statement, voidDeps: Seq[Expression]) class RefNotInitializedException(info: Info, mname: String, name: String, trace: Seq[Statement]) extends PassException( - s"$info : [module $mname] Reference $name is not fully initialized.\n" + + s"$info : [module $mname] Reference $name is not fully initialized.\n" + trace.map(s => s" ${get_info(s)} : ${s.serialize}").mkString("\n") ) private def getTrace(expr: WrappedExpression, voidExprs: Map[WrappedExpression, VoidExpr]): Seq[Statement] = { @tailrec def rec(e: WrappedExpression, map: Map[WrappedExpression, VoidExpr], trace: Seq[Statement]): Seq[Statement] = { - val voidExpr = map(e) + val voidExpr = map(e) val newTrace = voidExpr.stmt +: trace if (voidExpr.voidDeps.nonEmpty) rec(voidExpr.voidDeps.head, map, newTrace) else newTrace } @@ -62,7 +62,7 @@ object CheckInitialization extends Pass { case node: DefNode => val (hasVoid, voidDeps) = hasVoidExpr(node.value) if (hasVoid) { - val nodeRef = WRef(node.name, node.value.tpe, NodeKind, MALE) + val nodeRef = WRef(node.name, node.value.tpe, NodeKind, SourceFlow) voidExprs(nodeRef) = VoidExpr(node, voidDeps) } case sx => sx.foreach(checkInitS) diff --git a/src/main/scala/firrtl/passes/Checks.scala b/src/main/scala/firrtl/passes/Checks.scala index a17a5a2e..85ed7de0 100644 --- a/src/main/scala/firrtl/passes/Checks.scala +++ b/src/main/scala/firrtl/passes/Checks.scala @@ -221,12 +221,12 @@ trait CheckHighFormLike { // Search for ResetType Ports of direction def findBadResetTypePorts(m: DefModule, dir: Direction): Seq[(Port, Expression)] = { - val bad = to_gender(dir) + val bad = to_flow(dir) for { port <- m.ports - ref = WRef(port).copy(gender = to_gender(port.direction)) + ref = WRef(port).copy(flow = to_flow(port.direction)) expr <- create_exps(ref) - if ((expr.tpe == ResetType) && (gender(expr) == bad)) + if ((expr.tpe == ResetType) && (flow(expr) == bad)) } yield (port, expr) } @@ -544,31 +544,31 @@ object CheckTypes extends Pass { } } -object CheckGenders extends Pass { - type GenderMap = collection.mutable.HashMap[String, Gender] +object CheckFlows extends Pass { + type FlowMap = collection.mutable.HashMap[String, Flow] - implicit def toStr(g: Gender): String = g match { - case MALE => "source" - case FEMALE => "sink" - case UNKNOWNGENDER => "unknown" - case BIGENDER => "sourceOrSink" + implicit def toStr(g: Flow): String = g match { + case SourceFlow => "source" + case SinkFlow => "sink" + case UnknownFlow => "unknown" + case DuplexFlow => "duplex" } - class WrongGender(info:Info, mname: String, expr: String, wrong: Gender, right: Gender) extends PassException( + class WrongFlow(info:Info, mname: String, expr: String, wrong: Flow, right: Flow) extends PassException( s"$info: [module $mname] Expression $expr is used as a $wrong but can only be used as a $right.") def run (c:Circuit): Circuit = { val errors = new Errors() - def get_gender(e: Expression, genders: GenderMap): Gender = e match { - case (e: WRef) => genders(e.name) - case (e: WSubIndex) => get_gender(e.expr, genders) - case (e: WSubAccess) => get_gender(e.expr, genders) + def get_flow(e: Expression, flows: FlowMap): Flow = e match { + case (e: WRef) => flows(e.name) + case (e: WSubIndex) => get_flow(e.expr, flows) + case (e: WSubAccess) => get_flow(e.expr, flows) case (e: WSubField) => e.expr.tpe match {case t: BundleType => val f = (t.fields find (_.name == e.name)).get - times(get_gender(e.expr, genders), f.flip) + times(get_flow(e.expr, flows), f.flip) } - case _ => MALE + case _ => SourceFlow } def flip_q(t: Type): Boolean = { @@ -582,66 +582,83 @@ object CheckGenders extends Pass { flip_rec(t, Default) } - def check_gender(info:Info, mname: String, genders: GenderMap, desired: Gender)(e:Expression): Unit = { - val gender = get_gender(e,genders) - (gender, desired) match { - case (MALE, FEMALE) => - errors.append(new WrongGender(info, mname, e.serialize, desired, gender)) - case (FEMALE, MALE) => kind(e) match { + def check_flow(info:Info, mname: String, flows: FlowMap, desired: Flow)(e:Expression): Unit = { + val flow = get_flow(e,flows) + (flow, desired) match { + case (SourceFlow, SinkFlow) => + errors.append(new WrongFlow(info, mname, e.serialize, desired, flow)) + case (SinkFlow, SourceFlow) => kind(e) match { case PortKind | InstanceKind if !flip_q(e.tpe) => // OK! case _ => - errors.append(new WrongGender(info, mname, e.serialize, desired, gender)) + errors.append(new WrongFlow(info, mname, e.serialize, desired, flow)) } case _ => } } - def check_genders_e (info:Info, mname: String, genders: GenderMap)(e:Expression): Unit = { + def check_flows_e (info:Info, mname: String, flows: FlowMap)(e:Expression): Unit = { e match { - case e: Mux => e foreach check_gender(info, mname, genders, MALE) - case e: DoPrim => e.args foreach check_gender(info, mname, genders, MALE) + case e: Mux => e foreach check_flow(info, mname, flows, SourceFlow) + case e: DoPrim => e.args foreach check_flow(info, mname, flows, SourceFlow) case _ => } - e foreach check_genders_e(info, mname, genders) + e foreach check_flows_e(info, mname, flows) } - def check_genders_s(minfo: Info, mname: String, genders: GenderMap)(s: Statement): Unit = { + def check_flows_s(minfo: Info, mname: String, flows: FlowMap)(s: Statement): Unit = { val info = get_info(s) match { case NoInfo => minfo case x => x } s match { - case (s: DefWire) => genders(s.name) = BIGENDER - case (s: DefRegister) => genders(s.name) = BIGENDER - case (s: DefMemory) => genders(s.name) = MALE - case (s: WDefInstance) => genders(s.name) = MALE + case (s: DefWire) => flows(s.name) = DuplexFlow + case (s: DefRegister) => flows(s.name) = DuplexFlow + case (s: DefMemory) => flows(s.name) = SourceFlow + case (s: WDefInstance) => flows(s.name) = SourceFlow case (s: DefNode) => - check_gender(info, mname, genders, MALE)(s.value) - genders(s.name) = MALE + check_flow(info, mname, flows, SourceFlow)(s.value) + flows(s.name) = SourceFlow case (s: Connect) => - check_gender(info, mname, genders, FEMALE)(s.loc) - check_gender(info, mname, genders, MALE)(s.expr) + check_flow(info, mname, flows, SinkFlow)(s.loc) + check_flow(info, mname, flows, SourceFlow)(s.expr) case (s: Print) => - s.args foreach check_gender(info, mname, genders, MALE) - check_gender(info, mname, genders, MALE)(s.en) - check_gender(info, mname, genders, MALE)(s.clk) + s.args foreach check_flow(info, mname, flows, SourceFlow) + check_flow(info, mname, flows, SourceFlow)(s.en) + check_flow(info, mname, flows, SourceFlow)(s.clk) case (s: PartialConnect) => - check_gender(info, mname, genders, FEMALE)(s.loc) - check_gender(info, mname, genders, MALE)(s.expr) + check_flow(info, mname, flows, SinkFlow)(s.loc) + check_flow(info, mname, flows, SourceFlow)(s.expr) case (s: Conditionally) => - check_gender(info, mname, genders, MALE)(s.pred) + check_flow(info, mname, flows, SourceFlow)(s.pred) case (s: Stop) => - check_gender(info, mname, genders, MALE)(s.en) - check_gender(info, mname, genders, MALE)(s.clk) + check_flow(info, mname, flows, SourceFlow)(s.en) + check_flow(info, mname, flows, SourceFlow)(s.clk) case _ => } - s foreach check_genders_e(info, mname, genders) - s foreach check_genders_s(minfo, mname, genders) + s foreach check_flows_e(info, mname, flows) + s foreach check_flows_s(minfo, mname, flows) } for (m <- c.modules) { - val genders = new GenderMap - genders ++= (m.ports map (p => p.name -> to_gender(p.direction))) - m foreach check_genders_s(m.info, m.name, genders) + val flows = new FlowMap + flows ++= (m.ports map (p => p.name -> to_flow(p.direction))) + m foreach check_flows_s(m.info, m.name, flows) } errors.trigger() c } } + +@deprecated("Use 'CheckFlows'. This object will be removed in 1.3", "1.2") +object CheckGenders { + + implicit def toStr(g: Gender): String = g match { + case MALE => "source" + case FEMALE => "sink" + case UNKNOWNGENDER => "unknown" + case BIGENDER => "sourceOrSink" + } + + def run(c: Circuit): Circuit = CheckFlows.run(c) + + @deprecated("Use 'CheckFlows.WrongFlow'. This class will be removed in 1.3", "1.2") + class WrongGender(info:Info, mname: String, expr: String, wrong: Flow, right: Flow) extends PassException( + s"$info: [module $mname] Expression $expr is used as a $wrong but can only be used as a $right.") +} diff --git a/src/main/scala/firrtl/passes/CommonSubexpressionElimination.scala b/src/main/scala/firrtl/passes/CommonSubexpressionElimination.scala index f5b9d00c..3ba12b2d 100644 --- a/src/main/scala/firrtl/passes/CommonSubexpressionElimination.scala +++ b/src/main/scala/firrtl/passes/CommonSubexpressionElimination.scala @@ -13,10 +13,10 @@ object CommonSubexpressionElimination extends Pass { val nodes = collection.mutable.HashMap[String, Expression]() def eliminateNodeRef(e: Expression): Expression = e match { - case WRef(name, tpe, kind, gender) => nodes get name match { + case WRef(name, tpe, kind, flow) => nodes get name match { case Some(expression) => expressions get expression match { case Some(cseName) if cseName != name => - WRef(cseName, tpe, kind, gender) + WRef(cseName, tpe, kind, flow) case _ => e } case _ => e diff --git a/src/main/scala/firrtl/passes/ExpandWhens.scala b/src/main/scala/firrtl/passes/ExpandWhens.scala index a8e2f2ac..12aa9690 100644 --- a/src/main/scala/firrtl/passes/ExpandWhens.scala +++ b/src/main/scala/firrtl/passes/ExpandWhens.scala @@ -108,18 +108,18 @@ object ExpandWhens extends Pass { // Return self, unchanged case stmt @ (_: DefNode | EmptyStmt) => stmt case w: DefWire => - netlist ++= (getFemaleRefs(w.name, w.tpe, BIGENDER) map (ref => we(ref) -> WVoid)) + netlist ++= (getFemaleRefs(w.name, w.tpe, DuplexFlow) map (ref => we(ref) -> WVoid)) w case w: DefMemory => - netlist ++= (getFemaleRefs(w.name, MemPortUtils.memType(w), MALE) map (ref => we(ref) -> WVoid)) + netlist ++= (getFemaleRefs(w.name, MemPortUtils.memType(w), SourceFlow) map (ref => we(ref) -> WVoid)) w case w: WDefInstance => - netlist ++= (getFemaleRefs(w.name, w.tpe, MALE).map(ref => we(ref) -> WVoid)) + netlist ++= (getFemaleRefs(w.name, w.tpe, SourceFlow).map(ref => we(ref) -> WVoid)) w // Update netlist with self reference for each female reference // Return self, unchanged case r: DefRegister => - netlist ++= (getFemaleRefs(r.name, r.tpe, BIGENDER) map (ref => we(ref) -> ref)) + netlist ++= (getFemaleRefs(r.name, r.tpe, DuplexFlow) map (ref => we(ref) -> ref)) r // For value assignments, update netlist/attaches and return EmptyStmt case c: Connect => @@ -193,12 +193,12 @@ object ExpandWhens extends Pass { EmptyStmt case _: ValidIf | _: Mux | _: DoPrim => nodes get res match { case Some(name) => - netlist(lvalue) = WRef(name, res.tpe, NodeKind, MALE) + netlist(lvalue) = WRef(name, res.tpe, NodeKind, SourceFlow) EmptyStmt case None => val name = namespace.newTemp nodes(res) = name - netlist(lvalue) = WRef(name, res.tpe, NodeKind, MALE) + netlist(lvalue) = WRef(name, res.tpe, NodeKind, SourceFlow) DefNode(sx.info, name, res) } case _ => @@ -213,7 +213,7 @@ object ExpandWhens extends Pass { val netlist = new Netlist // Add ports to netlist netlist ++= (m.ports flatMap { case Port(_, name, dir, tpe) => - getFemaleRefs(name, tpe, to_gender(dir)) map (ref => we(ref) -> WVoid) + getFemaleRefs(name, tpe, to_flow(dir)) map (ref => we(ref) -> WVoid) }) val bodyx = expandWhens(netlist, Seq(netlist), one)(m.body) (netlist, simlist, attaches, bodyx, infoMap) @@ -221,13 +221,13 @@ object ExpandWhens extends Pass { /** Returns all references to all Female leaf subcomponents of a reference */ - private def getFemaleRefs(n: String, t: Type, g: Gender): Seq[Expression] = { + private def getFemaleRefs(n: String, t: Type, g: Flow): Seq[Expression] = { val exps = create_exps(WRef(n, t, ExpKind, g)) exps.flatMap { case exp => exp.tpe match { case AnalogType(w) => None - case _ => gender(exp) match { - case (BIGENDER | FEMALE) => Some(exp) + case _ => flow(exp) match { + case (DuplexFlow | SinkFlow) => Some(exp) case _ => None } } diff --git a/src/main/scala/firrtl/passes/InferWidths.scala b/src/main/scala/firrtl/passes/InferWidths.scala index 8f663afd..9c58da2c 100644 --- a/src/main/scala/firrtl/passes/InferWidths.scala +++ b/src/main/scala/firrtl/passes/InferWidths.scala @@ -182,18 +182,18 @@ class InferWidths extends Transform with ResolvedAnnotationPaths { rec(w) has } - + //; Forward solve //; Returns a solved list where each constraint undergoes: //; 1) Continuous Solving (using triangular solving) //; 2) Remove Cycles //; 3) Move to solved if not self-recursive val u = make_unique(l) - + //println("======== UNIQUE CONSTRAINTS ========") //for (x <- u) { println(x) } //println("====================================") - + val f = new ConstraintMap val o = ArrayBuffer[String]() for ((n, e) <- u) { @@ -219,10 +219,10 @@ class InferWidths extends Transform with ResolvedAnnotationPaths { o += n } } - + //println("Forward Solved Constraints") //for (x <- f) println(x) - + //; Backwards Solve val b = new ConstraintMap for (i <- (o.size - 1) to 0 by -1) { @@ -281,7 +281,7 @@ class InferWidths extends Transform with ResolvedAnnotationPaths { } def get_constraints_declared_type (t: Type): Type = t match { - case FixedType(_, p) => + case FixedType(_, p) => v += WGeq(p,IntWidth(0)) t case _ => t map get_constraints_declared_type @@ -293,7 +293,7 @@ class InferWidths extends Transform with ResolvedAnnotationPaths { val locs = create_exps(s.loc) val exps = create_exps(s.expr) v ++= locs.zip(exps).flatMap { case (locx, expx) => - to_flip(gender(locx)) match { + to_flip(flow(locx)) match { case Default => get_constraints_t(locx.tpe, expx.tpe)//WGeq(getWidth(locx), getWidth(expx)) case Flip => get_constraints_t(expx.tpe, locx.tpe)//WGeq(getWidth(expx), getWidth(locx)) } @@ -305,7 +305,7 @@ class InferWidths extends Transform with ResolvedAnnotationPaths { v ++= (ls flatMap {case (x, y) => val locx = locs(x) val expx = exps(y) - to_flip(gender(locx)) match { + to_flip(flow(locx)) match { case Default => get_constraints_t(locx.tpe, expx.tpe)//WGeq(getWidth(locx), getWidth(expx)) case Flip => get_constraints_t(expx.tpe, locx.tpe)//WGeq(getWidth(expx), getWidth(locx)) } @@ -317,7 +317,7 @@ class InferWidths extends Transform with ResolvedAnnotationPaths { get_constraints_t(UIntType(IntWidth(1)), s.reset.tpe)) } v ++= get_constraints_t(s.tpe, s.init.tpe) - case (s:Conditionally) => v ++= + case (s:Conditionally) => v ++= get_constraints_t(s.pred.tpe, UIntType(IntWidth(1))) ++ get_constraints_t(UIntType(IntWidth(1)), s.pred.tpe) case Attach(_, exprs) => diff --git a/src/main/scala/firrtl/passes/LowerTypes.scala b/src/main/scala/firrtl/passes/LowerTypes.scala index 8035c1ce..f52e1e6b 100644 --- a/src/main/scala/firrtl/passes/LowerTypes.scala +++ b/src/main/scala/firrtl/passes/LowerTypes.scala @@ -39,21 +39,21 @@ object LowerTypes extends Transform { } def loweredName(s: Seq[String]): String = s mkString delim def renameExps(renames: RenameMap, n: String, t: Type, root: String): Seq[String] = - renameExps(renames, WRef(n, t, ExpKind, UNKNOWNGENDER), root) + renameExps(renames, WRef(n, t, ExpKind, UnknownFlow), root) def renameExps(renames: RenameMap, n: String, t: Type): Seq[String] = - renameExps(renames, WRef(n, t, ExpKind, UNKNOWNGENDER), "") + renameExps(renames, WRef(n, t, ExpKind, UnknownFlow), "") def renameExps(renames: RenameMap, e: Expression, root: String): Seq[String] = e.tpe match { case (_: GroundType) => val name = root + loweredName(e) renames.rename(root + e.serialize, name) Seq(name) case (t: BundleType) => t.fields.flatMap { f => - val subNames = renameExps(renames, WSubField(e, f.name, f.tpe, times(gender(e), f.flip)), root) + val subNames = renameExps(renames, WSubField(e, f.name, f.tpe, times(flow(e), f.flip)), root) renames.rename(root + e.serialize, subNames) subNames } case (t: VectorType) => (0 until t.size).flatMap { i => - val subNames = renameExps(renames, WSubIndex(e, i, t.tpe,gender(e)), root) + val subNames = renameExps(renames, WSubIndex(e, i, t.tpe,flow(e)), root) renames.rename(root + e.serialize, subNames) subNames } @@ -67,14 +67,14 @@ object LowerTypes extends Transform { renames.rename(hiRef.serialize, loRef.serialize) Seq(loRef.serialize) case (t: BundleType) => t.fields.foldLeft(Seq[String]()){(names, f) => - val subNames = renameMemExps(renames, WSubField(e, f.name, f.tpe, times(gender(e), f.flip)), portAndField) + val subNames = renameMemExps(renames, WSubField(e, f.name, f.tpe, times(flow(e), f.flip)), portAndField) val (mem, tail) = splitRef(e) val hiRef = mergeRef(mem, mergeRef(portAndField, tail)) renames.rename(hiRef.serialize, subNames) names ++ subNames } case (t: VectorType) => (0 until t.size).foldLeft(Seq[String]()){(names, i) => - val subNames = renameMemExps(renames, WSubIndex(e, i, t.tpe,gender(e)), portAndField) + val subNames = renameMemExps(renames, WSubIndex(e, i, t.tpe,flow(e)), portAndField) val (mem, tail) = splitRef(e) val hiRef = mergeRef(mem, mergeRef(portAndField, tail)) renames.rename(hiRef.serialize, subNames) @@ -116,7 +116,7 @@ object LowerTypes extends Transform { case _: GroundType => Seq(e) case memType => create_exps(mem.name, memType) map { e => val loMemName = loweredName(e) - val loMem = WRef(loMemName, UnknownType, kind(mem), UNKNOWNGENDER) + val loMem = WRef(loMemName, UnknownType, kind(mem), UnknownFlow) mergeRef(loMem, mergeRef(port, field)) } } @@ -128,7 +128,7 @@ object LowerTypes extends Transform { case Some(ex) => val loMemExp = mergeRef(mem, ex) val loMemName = loweredName(loMemExp) - WRef(loMemName, UnknownType, kind(mem), UNKNOWNGENDER) + WRef(loMemName, UnknownType, kind(mem), UnknownFlow) case None => mem } Seq(mergeRef(loMem, mergeRef(port, field))) @@ -143,15 +143,15 @@ object LowerTypes extends Transform { case InstanceKind => val (root, tail) = splitRef(e) val name = loweredName(tail) - WSubField(root, name, e.tpe, gender(e)) + WSubField(root, name, e.tpe, flow(e)) case MemKind => val exps = lowerTypesMemExp(memDataTypeMap, info, mname)(e) exps.size match { case 1 => exps.head - case _ => error("Error! lowerTypesExp called on MemKind " + + case _ => error("Error! lowerTypesExp called on MemKind " + "SubField that needs to be expanded!")(info, mname) } - case _ => WRef(loweredName(e), e.tpe, kind(e), gender(e)) + case _ => WRef(loweredName(e), e.tpe, kind(e), flow(e)) } case e: Mux => e map lowerTypesExp(memDataTypeMap, info, mname) case e: ValidIf => e map lowerTypesExp(memDataTypeMap, info, mname) @@ -164,11 +164,11 @@ object LowerTypes extends Transform { s map lowerTypesStmt(memDataTypeMap, info, mname, renames) match { case s: DefWire => s.tpe match { case _: GroundType => s - case _ => + case _ => val exps = create_exps(s.name, s.tpe) val names = exps map loweredName renameExps(renames, s.name, s.tpe) - Block((exps zip names) map { case (e, n) => + Block((exps zip names) map { case (e, n) => DefWire(s.info, n, e.tpe) }) } @@ -190,9 +190,9 @@ object LowerTypes extends Transform { case t: BundleType => val fieldsx = t.fields flatMap { f => renameExps(renames, f.name, f.tpe, s"${sx.name}.") - create_exps(WRef(f.name, f.tpe, ExpKind, times(f.flip, MALE))) map { e => - // Flip because inst genders are reversed from Module type - Field(loweredName(e), swap(to_flip(gender(e))), e.tpe) + create_exps(WRef(f.name, f.tpe, ExpKind, times(f.flip, SourceFlow))) map { e => + // Flip because inst flows are reversed from Module type + Field(loweredName(e), swap(to_flip(flow(e))), e.tpe) } } WDefInstance(sx.info, sx.name, sx.module, BundleType(fieldsx)) @@ -262,11 +262,11 @@ object LowerTypes extends Transform { renames.setModule(m.name) // Lower Ports val portsx = m.ports flatMap { p => - val exps = create_exps(WRef(p.name, p.tpe, PortKind, to_gender(p.direction))) + val exps = create_exps(WRef(p.name, p.tpe, PortKind, to_flow(p.direction))) val names = exps map loweredName renameExps(renames, p.name, p.tpe) (exps zip names) map { case (e, n) => - Port(p.info, n, to_dir(gender(e)), e.tpe) + Port(p.info, n, to_dir(flow(e)), e.tpe) } } m match { @@ -285,4 +285,3 @@ object LowerTypes extends Transform { CircuitState(result, outputForm, state.annotations, Some(renames)) } } - diff --git a/src/main/scala/firrtl/passes/Passes.scala b/src/main/scala/firrtl/passes/Passes.scala index 1428ea5f..9a644dc8 100644 --- a/src/main/scala/firrtl/passes/Passes.scala +++ b/src/main/scala/firrtl/passes/Passes.scala @@ -48,10 +48,10 @@ class Errors { // These should be distributed into separate files object ToWorkingIR extends Pass { def toExp(e: Expression): Expression = e map toExp match { - case ex: Reference => WRef(ex.name, ex.tpe, UnknownKind, UNKNOWNGENDER) - case ex: SubField => WSubField(ex.expr, ex.name, ex.tpe, UNKNOWNGENDER) - case ex: SubIndex => WSubIndex(ex.expr, ex.value, ex.tpe, UNKNOWNGENDER) - case ex: SubAccess => WSubAccess(ex.expr, ex.index, ex.tpe, UNKNOWNGENDER) + case ex: Reference => WRef(ex.name, ex.tpe, UnknownKind, UnknownFlow) + case ex: SubField => WSubField(ex.expr, ex.name, ex.tpe, UnknownFlow) + case ex: SubIndex => WSubIndex(ex.expr, ex.value, ex.tpe, UnknownFlow) + case ex: SubAccess => WSubAccess(ex.expr, ex.index, ex.tpe, UnknownFlow) case ex => ex // This might look like a case to use case _ => e, DO NOT! } @@ -69,26 +69,26 @@ object PullMuxes extends Pass { def pull_muxes_e(e: Expression): Expression = e map pull_muxes_e match { case ex: WSubField => ex.expr match { case exx: Mux => Mux(exx.cond, - WSubField(exx.tval, ex.name, ex.tpe, ex.gender), - WSubField(exx.fval, ex.name, ex.tpe, ex.gender), ex.tpe) + WSubField(exx.tval, ex.name, ex.tpe, ex.flow), + WSubField(exx.fval, ex.name, ex.tpe, ex.flow), ex.tpe) case exx: ValidIf => ValidIf(exx.cond, - WSubField(exx.value, ex.name, ex.tpe, ex.gender), ex.tpe) + WSubField(exx.value, ex.name, ex.tpe, ex.flow), ex.tpe) case _ => ex // case exx => exx causes failed tests } case ex: WSubIndex => ex.expr match { case exx: Mux => Mux(exx.cond, - WSubIndex(exx.tval, ex.value, ex.tpe, ex.gender), - WSubIndex(exx.fval, ex.value, ex.tpe, ex.gender), ex.tpe) + WSubIndex(exx.tval, ex.value, ex.tpe, ex.flow), + WSubIndex(exx.fval, ex.value, ex.tpe, ex.flow), ex.tpe) case exx: ValidIf => ValidIf(exx.cond, - WSubIndex(exx.value, ex.value, ex.tpe, ex.gender), ex.tpe) + WSubIndex(exx.value, ex.value, ex.tpe, ex.flow), ex.tpe) case _ => ex // case exx => exx causes failed tests } case ex: WSubAccess => ex.expr match { case exx: Mux => Mux(exx.cond, - WSubAccess(exx.tval, ex.index, ex.tpe, ex.gender), - WSubAccess(exx.fval, ex.index, ex.tpe, ex.gender), ex.tpe) + WSubAccess(exx.tval, ex.index, ex.tpe, ex.flow), + WSubAccess(exx.fval, ex.index, ex.tpe, ex.flow), ex.tpe) case exx: ValidIf => ValidIf(exx.cond, - WSubAccess(exx.value, ex.index, ex.tpe, ex.gender), ex.tpe) + WSubAccess(exx.value, ex.index, ex.tpe, ex.flow), ex.tpe) case _ => ex // case exx => exx causes failed tests } case ex => ex @@ -105,29 +105,29 @@ object PullMuxes extends Pass { object ExpandConnects extends Pass { def run(c: Circuit): Circuit = { def expand_connects(m: Module): Module = { - val genders = collection.mutable.LinkedHashMap[String,Gender]() + val flows = collection.mutable.LinkedHashMap[String,Flow]() def expand_s(s: Statement): Statement = { - def set_gender(e: Expression): Expression = e map set_gender match { - case ex: WRef => WRef(ex.name, ex.tpe, ex.kind, genders(ex.name)) + def set_flow(e: Expression): Expression = e map set_flow match { + case ex: WRef => WRef(ex.name, ex.tpe, ex.kind, flows(ex.name)) case ex: WSubField => val f = get_field(ex.expr.tpe, ex.name) - val genderx = times(gender(ex.expr), f.flip) - WSubField(ex.expr, ex.name, ex.tpe, genderx) - case ex: WSubIndex => WSubIndex(ex.expr, ex.value, ex.tpe, gender(ex.expr)) - case ex: WSubAccess => WSubAccess(ex.expr, ex.index, ex.tpe, gender(ex.expr)) + val flowx = times(flow(ex.expr), f.flip) + WSubField(ex.expr, ex.name, ex.tpe, flowx) + case ex: WSubIndex => WSubIndex(ex.expr, ex.value, ex.tpe, flow(ex.expr)) + case ex: WSubAccess => WSubAccess(ex.expr, ex.index, ex.tpe, flow(ex.expr)) case ex => ex } s match { - case sx: DefWire => genders(sx.name) = BIGENDER; sx - case sx: DefRegister => genders(sx.name) = BIGENDER; sx - case sx: WDefInstance => genders(sx.name) = MALE; sx - case sx: DefMemory => genders(sx.name) = MALE; sx - case sx: DefNode => genders(sx.name) = MALE; sx + case sx: DefWire => flows(sx.name) = DuplexFlow; sx + case sx: DefRegister => flows(sx.name) = DuplexFlow; sx + case sx: WDefInstance => flows(sx.name) = SourceFlow; sx + case sx: DefMemory => flows(sx.name) = SourceFlow; sx + case sx: DefNode => flows(sx.name) = SourceFlow; sx case sx: IsInvalid => val invalids = create_exps(sx.expr).flatMap { case expx => - gender(set_gender(expx)) match { - case BIGENDER => Some(IsInvalid(sx.info, expx)) - case FEMALE => Some(IsInvalid(sx.info, expx)) + flow(set_flow(expx)) match { + case DuplexFlow => Some(IsInvalid(sx.info, expx)) + case SinkFlow => Some(IsInvalid(sx.info, expx)) case _ => None } } @@ -140,7 +140,7 @@ object ExpandConnects extends Pass { val locs = create_exps(sx.loc) val exps = create_exps(sx.expr) Block(locs.zip(exps).map { case (locx, expx) => - to_flip(gender(locx)) match { + to_flip(flow(locx)) match { case Default => Connect(sx.info, locx, expx) case Flip => Connect(sx.info, expx, locx) } @@ -153,7 +153,7 @@ object ExpandConnects extends Pass { locs(x).tpe match { case AnalogType(_) => Attach(sx.info, Seq(locs(x), exps(y))) case _ => - to_flip(gender(locs(x))) match { + to_flip(flow(locs(x))) match { case Default => Connect(sx.info, locs(x), exps(y)) case Flip => Connect(sx.info, exps(y), locs(x)) } @@ -164,7 +164,7 @@ object ExpandConnects extends Pass { } } - m.ports.foreach { p => genders(p.name) = to_gender(p.direction) } + m.ports.foreach { p => flows(p.name) = to_flow(p.direction) } Module(m.info, m.name, m.ports, expand_s(m.body)) } @@ -302,13 +302,13 @@ object VerilogPrep extends Pass { def run(c: Circuit): Circuit = { def lowerE(e: Expression): Expression = e match { case (_: WRef | _: WSubField) if kind(e) == InstanceKind => - WRef(LowerTypes.loweredName(e), e.tpe, kind(e), gender(e)) + WRef(LowerTypes.loweredName(e), e.tpe, kind(e), flow(e)) case _ => e map lowerE } def lowerS(attachMap: AttachSourceMap)(s: Statement): Statement = s match { case WDefInstance(info, name, module, tpe) => - val portRefs = create_exps(WRef(name, tpe, ExpKind, MALE)) + val portRefs = create_exps(WRef(name, tpe, ExpKind, SourceFlow)) val (portCons, wires) = portRefs.map { p => attachMap.get(p) match { // If it has a source in attachMap use that diff --git a/src/main/scala/firrtl/passes/RemoveAccesses.scala b/src/main/scala/firrtl/passes/RemoveAccesses.scala index 2cad4c36..1c2dc096 100644 --- a/src/main/scala/firrtl/passes/RemoveAccesses.scala +++ b/src/main/scala/firrtl/passes/RemoveAccesses.scala @@ -85,7 +85,7 @@ class RemoveAccesses extends Pass { def onStmt(s: Statement): Statement = { def create_temp(e: Expression): (Statement, Expression) = { val n = namespace.newName(niceName(e)) - (DefWire(get_info(s), n, e.tpe), WRef(n, e.tpe, kind(e), gender(e))) + (DefWire(get_info(s), n, e.tpe), WRef(n, e.tpe, kind(e), flow(e))) } /** Replaces a subaccess in a given male expression @@ -134,7 +134,7 @@ class RemoveAccesses extends Pass { * Otherwise, map to children. */ def fixMale(e: Expression): Expression = e match { - case w: WSubAccess => removeMale(WSubAccess(w.expr, fixMale(w.index), w.tpe, w.gender)) + case w: WSubAccess => removeMale(WSubAccess(w.expr, fixMale(w.index), w.tpe, w.flow)) //case w: WSubIndex => removeMale(w) //case w: WSubField => removeMale(w) case x => x map fixMale @@ -145,7 +145,7 @@ class RemoveAccesses extends Pass { * Otherwise, map to children. */ def fixFemale(e: Expression): Expression = e match { - case w: WSubAccess => WSubAccess(fixFemale(w.expr), fixMale(w.index), w.tpe, w.gender) + case w: WSubAccess => WSubAccess(fixFemale(w.expr), fixMale(w.index), w.tpe, w.flow) case x => x map fixFemale } @@ -159,7 +159,7 @@ class RemoveAccesses extends Pass { } Module(m.info, m.name, m.ports, squashEmpty(onStmt(m.body))) } - + c copy (modules = c.modules map { case m: ExtModule => m case m: Module => remove_m(m) diff --git a/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala b/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala index 0ccb0b34..d0498cf0 100644 --- a/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala +++ b/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala @@ -178,41 +178,41 @@ object RemoveCHIRRTL extends Transform { var has_write_mport = false var has_readwrite_mport: Option[Expression] = None var has_read_mport: Option[Expression] = None - def remove_chirrtl_e(g: Gender)(e: Expression): Expression = e match { + def remove_chirrtl_e(g: Flow)(e: Expression): Expression = e match { case Reference(name, tpe) => refs get name match { case Some(p) => g match { - case FEMALE => + case SinkFlow => has_write_mport = true if (p.rdwrite) has_readwrite_mport = Some(SubField(p.exp, "wmode", BoolType)) SubField(p.exp, p.female, tpe) - case MALE => + case SourceFlow => SubField(p.exp, p.male, tpe) } case None => g match { - case FEMALE => raddrs get name match { + case SinkFlow => raddrs get name match { case Some(en) => has_read_mport = Some(en) ; e case None => e } - case MALE => e + case SourceFlow => e } } case SubAccess(expr, index, tpe) => SubAccess( - remove_chirrtl_e(g)(expr), remove_chirrtl_e(MALE)(index), tpe) + remove_chirrtl_e(g)(expr), remove_chirrtl_e(SourceFlow)(index), tpe) case ex => ex map remove_chirrtl_e(g) } s match { case DefNode(info, name, value) => - val valuex = remove_chirrtl_e(MALE)(value) + val valuex = remove_chirrtl_e(SourceFlow)(value) val sx = DefNode(info, name, valuex) // Check node is used for read port address - remove_chirrtl_e(FEMALE)(Reference(name, value.tpe)) + remove_chirrtl_e(SinkFlow)(Reference(name, value.tpe)) has_read_mport match { case None => sx case Some(en) => Block(Seq(sx, Connect(info, en, one))) } case Connect(info, loc, expr) => - val rocx = remove_chirrtl_e(MALE)(expr) - val locx = remove_chirrtl_e(FEMALE)(loc) + val rocx = remove_chirrtl_e(SourceFlow)(expr) + val locx = remove_chirrtl_e(SinkFlow)(loc) val sx = Connect(info, locx, rocx) val stmts = ArrayBuffer[Statement]() has_read_mport match { @@ -229,8 +229,8 @@ object RemoveCHIRRTL extends Transform { } if (stmts.isEmpty) sx else Block(sx +: stmts) case PartialConnect(info, loc, expr) => - val locx = remove_chirrtl_e(FEMALE)(loc) - val rocx = remove_chirrtl_e(MALE)(expr) + val locx = remove_chirrtl_e(SinkFlow)(loc) + val rocx = remove_chirrtl_e(SourceFlow)(expr) val sx = PartialConnect(info, locx, rocx) val stmts = ArrayBuffer[Statement]() has_read_mport match { @@ -247,7 +247,7 @@ object RemoveCHIRRTL extends Transform { } } if (stmts.isEmpty) sx else Block(sx +: stmts) - case sx => sx map remove_chirrtl_s(refs, raddrs) map remove_chirrtl_e(MALE) + case sx => sx map remove_chirrtl_s(refs, raddrs) map remove_chirrtl_e(SourceFlow) } } diff --git a/src/main/scala/firrtl/passes/Resolves.scala b/src/main/scala/firrtl/passes/Resolves.scala index e4a06525..24dcda4a 100644 --- a/src/main/scala/firrtl/passes/Resolves.scala +++ b/src/main/scala/firrtl/passes/Resolves.scala @@ -22,7 +22,7 @@ object ResolveKinds extends Pass { case sx: WDefInstance => kinds(sx.name) = InstanceKind case sx: DefMemory => kinds(sx.name) = MemKind case _ => - } + } s map find_stmt(kinds) } @@ -40,14 +40,14 @@ object ResolveKinds extends Pass { map find_stmt(kinds) map resolve_stmt(kinds)) } - + def run(c: Circuit): Circuit = c copy (modules = c.modules map resolve_kinds) } -object ResolveGenders extends Pass { - def resolve_e(g: Gender)(e: Expression): Expression = e match { - case ex: WRef => ex copy (gender = g) +object ResolveFlows extends Pass { + def resolve_e(g: Flow)(e: Expression): Expression = e match { + case ex: WRef => ex copy (flow = g) case WSubField(exp, name, tpe, _) => WSubField( Utils.field_flip(exp.tpe, name) match { case Default => resolve_e(g)(exp) @@ -56,25 +56,36 @@ object ResolveGenders extends Pass { case WSubIndex(exp, value, tpe, _) => WSubIndex(resolve_e(g)(exp), value, tpe, g) case WSubAccess(exp, index, tpe, _) => - WSubAccess(resolve_e(g)(exp), resolve_e(MALE)(index), tpe, g) + WSubAccess(resolve_e(g)(exp), resolve_e(SourceFlow)(index), tpe, g) case _ => e map resolve_e(g) } - + def resolve_s(s: Statement): Statement = s match { //TODO(azidar): pretty sure don't need to do anything for Attach, but not positive... case IsInvalid(info, expr) => - IsInvalid(info, resolve_e(FEMALE)(expr)) + IsInvalid(info, resolve_e(SinkFlow)(expr)) case Connect(info, loc, expr) => - Connect(info, resolve_e(FEMALE)(loc), resolve_e(MALE)(expr)) + Connect(info, resolve_e(SinkFlow)(loc), resolve_e(SourceFlow)(expr)) case PartialConnect(info, loc, expr) => - PartialConnect(info, resolve_e(FEMALE)(loc), resolve_e(MALE)(expr)) - case sx => sx map resolve_e(MALE) map resolve_s + PartialConnect(info, resolve_e(SinkFlow)(loc), resolve_e(SourceFlow)(expr)) + case sx => sx map resolve_e(SourceFlow) map resolve_s } - def resolve_gender(m: DefModule): DefModule = m map resolve_s + def resolve_flow(m: DefModule): DefModule = m map resolve_s def run(c: Circuit): Circuit = - c copy (modules = c.modules map resolve_gender) + c copy (modules = c.modules map resolve_flow) +} + +@deprecated("Use 'ResolveFlows'. This will be removed in 1.3", "1.2") +object ResolveGenders { + + def run(c: Circuit): Circuit = ResolveFlows.run(c) + + def resolve_e(g: Gender)(e: Expression): Expression = ResolveFlows.resolve_e(g)(e) + + def resolve_s(s: Statement): Statement = ResolveFlows.resolve_s(s) + } object CInferMDir extends Pass { @@ -111,7 +122,7 @@ object CInferMDir extends Pass { case e => e map infer_mdir_e(mports, dir) } - def infer_mdir_s(mports: MPortDirMap)(s: Statement): Statement = s match { + def infer_mdir_s(mports: MPortDirMap)(s: Statement): Statement = s match { case sx: CDefMPort => mports(sx.name) = sx.direction sx map infer_mdir_e(mports, MRead) @@ -125,17 +136,17 @@ object CInferMDir extends Pass { sx case sx => sx map infer_mdir_s(mports) map infer_mdir_e(mports, MRead) } - - def set_mdir_s(mports: MPortDirMap)(s: Statement): Statement = s match { + + def set_mdir_s(mports: MPortDirMap)(s: Statement): Statement = s match { case sx: CDefMPort => sx copy (direction = mports(sx.name)) case sx => sx map set_mdir_s(mports) } - + def infer_mdir(m: DefModule): DefModule = { val mports = new MPortDirMap m map infer_mdir_s(mports) map set_mdir_s(mports) } - + def run(c: Circuit): Circuit = c copy (modules = c.modules map infer_mdir) } diff --git a/src/main/scala/firrtl/passes/SplitExpressions.scala b/src/main/scala/firrtl/passes/SplitExpressions.scala index a32f5366..de955c9a 100644 --- a/src/main/scala/firrtl/passes/SplitExpressions.scala +++ b/src/main/scala/firrtl/passes/SplitExpressions.scala @@ -5,7 +5,7 @@ package passes import firrtl.ir._ import firrtl.Mappers._ -import firrtl.Utils.{kind, gender, get_info} +import firrtl.Utils.{kind, flow, get_info} // Datastructures import scala.collection.mutable @@ -23,15 +23,15 @@ object SplitExpressions extends Pass { case e: DoPrim => val name = namespace.newTemp v += DefNode(get_info(s), name, e) - WRef(name, e.tpe, kind(e), gender(e)) + WRef(name, e.tpe, kind(e), flow(e)) case e: Mux => val name = namespace.newTemp v += DefNode(get_info(s), name, e) - WRef(name, e.tpe, kind(e), gender(e)) + WRef(name, e.tpe, kind(e), flow(e)) case e: ValidIf => val name = namespace.newTemp v += DefNode(get_info(s), name, e) - WRef(name, e.tpe, kind(e), gender(e)) + WRef(name, e.tpe, kind(e), flow(e)) case _ => e } diff --git a/src/main/scala/firrtl/passes/Uniquify.scala b/src/main/scala/firrtl/passes/Uniquify.scala index 52a2f95e..978ccc66 100644 --- a/src/main/scala/firrtl/passes/Uniquify.scala +++ b/src/main/scala/firrtl/passes/Uniquify.scala @@ -155,7 +155,7 @@ object Uniquify extends Transform { case e: WRef => if (m.contains(e.name)) { val node = m(e.name) - (WRef(node.name, e.tpe, e.kind, e.gender), node.elts) + (WRef(node.name, e.tpe, e.kind, e.flow), node.elts) } else (e, Map()) case e: WSubField => @@ -167,14 +167,14 @@ object Uniquify extends Transform { } else { (e.name, Map[String, NameMapNode]()) } - (WSubField(subExp, retName, e.tpe, e.gender), retMap) + (WSubField(subExp, retName, e.tpe, e.flow), retMap) case e: WSubIndex => val (subExp, subMap) = rec(e.expr, m) - (WSubIndex(subExp, e.value, e.tpe, e.gender), subMap) + (WSubIndex(subExp, e.value, e.tpe, e.flow), subMap) case e: WSubAccess => val (subExp, subMap) = rec(e.expr, m) val index = uniquifyNamesExp(e.index, map) - (WSubAccess(subExp, index, e.tpe, e.gender), subMap) + (WSubAccess(subExp, index, e.tpe, e.flow), subMap) case (_: UIntLiteral | _: SIntLiteral) => (exp, m) case (_: Mux | _: ValidIf | _: DoPrim) => (exp map ((e: Expression) => uniquifyNamesExp(e, map)), m) @@ -265,7 +265,7 @@ object Uniquify extends Transform { if (nameMap.contains(sx.name)) { val node = nameMap(sx.name) val newType = uniquifyNamesType(sx.tpe, node.elts) - (Utils.create_exps(sx.name, sx.tpe) zip Utils.create_exps(node.name, newType)) foreach { + (Utils.create_exps(sx.name, sx.tpe) zip Utils.create_exps(node.name, newType)) foreach { case (from, to) => renames.rename(from.serialize, to.serialize) } DefWire(sx.info, node.name, newType) @@ -382,4 +382,3 @@ object Uniquify extends Transform { CircuitState(result, outputForm, state.annotations, Some(renames)) } } - diff --git a/src/main/scala/firrtl/passes/VerilogModulusCleanup.scala b/src/main/scala/firrtl/passes/VerilogModulusCleanup.scala index 330ca497..fdc81797 100644 --- a/src/main/scala/firrtl/passes/VerilogModulusCleanup.scala +++ b/src/main/scala/firrtl/passes/VerilogModulusCleanup.scala @@ -47,11 +47,11 @@ object VerilogModulusCleanup extends Pass { def removeRem(e: Expression): Expression = e match { case e: DoPrim => e.op match { - case Rem => + case Rem => val name = namespace.newTemp val newType = e mapType verilogRemWidth(e) v += DefNode(get_info(s), name, e mapType verilogRemWidth(e)) - val remRef = WRef(name, newType.tpe, kind(e), gender(e)) + val remRef = WRef(name, newType.tpe, kind(e), flow(e)) val remWidth = bitWidth(e.tpe) DoPrim(Bits, Seq(remRef), Seq(remWidth - 1, BigInt(0)), e.tpe) case _ => e diff --git a/src/main/scala/firrtl/passes/ZeroWidth.scala b/src/main/scala/firrtl/passes/ZeroWidth.scala index 6a79fe9a..83fc1b6b 100644 --- a/src/main/scala/firrtl/passes/ZeroWidth.scala +++ b/src/main/scala/firrtl/passes/ZeroWidth.scala @@ -63,14 +63,14 @@ object ZeroWidth extends Transform { } case BundleType(fields) => if (fields.isEmpty) List(expr) - else fields.flatMap(f => findRemovable(WSubField(expr, f.name, f.tpe, MALE), f.tpe)) + else fields.flatMap(f => findRemovable(WSubField(expr, f.name, f.tpe, SourceFlow), f.tpe)) case VectorType(vtpe, size) => if (size == 0) List(expr) else { // Only invoke findRemovable multiple times if a zero-width element is found - val es0 = findRemovable(WSubIndex(expr, 0, vtpe, MALE), vtpe) + val es0 = findRemovable(WSubIndex(expr, 0, vtpe, SourceFlow), vtpe) if (es0.isEmpty) es0 else { - es0 ++ (1 until size).flatMap(i => findRemovable(WSubIndex(expr, i, vtpe, MALE), vtpe)) + es0 ++ (1 until size).flatMap(i => findRemovable(WSubIndex(expr, i, vtpe, SourceFlow), vtpe)) } } } diff --git a/src/main/scala/firrtl/passes/clocklist/ClockListUtils.scala b/src/main/scala/firrtl/passes/clocklist/ClockListUtils.scala index f92a878e..b77629fc 100644 --- a/src/main/scala/firrtl/passes/clocklist/ClockListUtils.scala +++ b/src/main/scala/firrtl/passes/clocklist/ClockListUtils.scala @@ -20,8 +20,8 @@ object ClockListUtils { } val sourceList = moduleMap(lin.name) match { case ExtModule(i, n, ports, dn, p) => - val portExps = ports.flatMap{p => create_exps(WRef(p.name, p.tpe, PortKind, to_gender(p.direction)))} - portExps.filter(e => (e.tpe == ClockType) && (gender(e) == FEMALE)).map(_.serialize) + val portExps = ports.flatMap{p => create_exps(WRef(p.name, p.tpe, PortKind, to_flow(p.direction)))} + portExps.filter(e => (e.tpe == ClockType) && (flow(e) == SinkFlow)).map(_.serialize) case _ => Nil } val sx = sourceList ++ s diff --git a/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala b/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala index 44f45985..1e88a9b0 100644 --- a/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala +++ b/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala @@ -160,7 +160,7 @@ class InferReadWrite extends Transform with SeqTransformBased with HasShellOptio CheckInitialization, InferTypes, ResolveKinds, - ResolveGenders + ResolveFlows ) def execute(state: CircuitState): CircuitState = { val runTransform = state.annotations.contains(InferReadWriteAnnotation) diff --git a/src/main/scala/firrtl/passes/memlib/MemUtils.scala b/src/main/scala/firrtl/passes/memlib/MemUtils.scala index bf8b9401..b16a7424 100644 --- a/src/main/scala/firrtl/passes/memlib/MemUtils.scala +++ b/src/main/scala/firrtl/passes/memlib/MemUtils.scala @@ -29,11 +29,11 @@ object toBitMask { (mask.tpe, dataType) match { case (mt: VectorType, dt: VectorType) => seqCat((0 until mt.size).reverse map { i => - hiermask(WSubIndex(mask, i, mt.tpe, UNKNOWNGENDER), dt.tpe) + hiermask(WSubIndex(mask, i, mt.tpe, UnknownFlow), dt.tpe) }) case (mt: BundleType, dt: BundleType) => seqCat((mt.fields zip dt.fields) map { case (mf, df) => - hiermask(WSubField(mask, mf.name, mf.tpe, UNKNOWNGENDER), df.tpe) + hiermask(WSubField(mask, mf.name, mf.tpe, UnknownFlow), df.tpe) }) case (UIntType(width), dt: GroundType) if width == IntWidth(BigInt(1)) => seqCat(List.fill(bitWidth(dt).intValue)(mask)) @@ -80,9 +80,9 @@ object MemPortUtils { } def memPortField(s: DefMemory, p: String, f: String): Expression = { - val mem = WRef(s.name, memType(s), MemKind, UNKNOWNGENDER) + val mem = WRef(s.name, memType(s), MemKind, UnknownFlow) val t1 = field_type(mem.tpe, p) val t2 = field_type(t1, f) - WSubField(WSubField(mem, p, t1, UNKNOWNGENDER), f, t2, UNKNOWNGENDER) + WSubField(WSubField(mem, p, t1, UnknownFlow), f, t2, UnknownFlow) } } diff --git a/src/main/scala/firrtl/passes/memlib/ReplaceMemTransform.scala b/src/main/scala/firrtl/passes/memlib/ReplaceMemTransform.scala index 6ccfd601..f3ef917b 100644 --- a/src/main/scala/firrtl/passes/memlib/ReplaceMemTransform.scala +++ b/src/main/scala/firrtl/passes/memlib/ReplaceMemTransform.scala @@ -126,7 +126,7 @@ class ReplSeqMem extends Transform with HasShellOptions { new SimpleMidTransform(InferTypes), Uniquify, new SimpleMidTransform(ResolveKinds), - new SimpleMidTransform(ResolveGenders)) + new SimpleMidTransform(ResolveFlows)) def execute(state: CircuitState): CircuitState = { val annos = state.annotations.collect { case a: ReplSeqMemAnnotation => a } diff --git a/src/main/scala/firrtl/passes/memlib/ResolveMaskGranularity.scala b/src/main/scala/firrtl/passes/memlib/ResolveMaskGranularity.scala index b552470d..41c47dce 100644 --- a/src/main/scala/firrtl/passes/memlib/ResolveMaskGranularity.scala +++ b/src/main/scala/firrtl/passes/memlib/ResolveMaskGranularity.scala @@ -38,14 +38,14 @@ object AnalysisUtils { /** Find a connection LHS's origin from a module's list of node-to-node connections * regardless of whether constant propagation has been run. * Will search past trivial primop/mux's which do not affect its origin. - * Limitations: + * Limitations: * - Only works in a module (stops @ module inputs) * - Only does trivial primop/mux's (is not complete) * TODO(shunshou): implement more equivalence cases (i.e. a + 0 = a) */ def getOrigin(connects: Connects, s: String): Expression = - getOrigin(connects)(WRef(s, UnknownType, ExpKind, UNKNOWNGENDER)) - def getOrigin(connects: Connects)(e: Expression): Expression = e match { + getOrigin(connects)(WRef(s, UnknownType, ExpKind, UnknownFlow)) + def getOrigin(connects: Connects)(e: Expression): Expression = e match { case Mux(cond, tv, fv, _) => val fvOrigin = getOrigin(connects)(fv) val tvOrigin = getOrigin(connects)(tv) @@ -58,12 +58,12 @@ object AnalysisUtils { else e case DoPrim(PrimOps.Or, args, consts, tpe) if args exists (weq(_, one)) => one case DoPrim(PrimOps.And, args, consts, tpe) if args exists (weq(_, zero)) => zero - case DoPrim(PrimOps.Bits, args, Seq(msb, lsb), tpe) => + case DoPrim(PrimOps.Bits, args, Seq(msb, lsb), tpe) => val extractionWidth = (msb - lsb) + 1 val nodeWidth = bitWidth(args.head.tpe) // if you're extracting the full bitwidth, then keep searching for origin if (nodeWidth == extractionWidth) getOrigin(connects)(args.head) else e - case DoPrim((PrimOps.AsUInt | PrimOps.AsSInt | PrimOps.AsClock), args, _, _) => + case DoPrim((PrimOps.AsUInt | PrimOps.AsSInt | PrimOps.AsClock), args, _, _) => getOrigin(connects)(args.head) // It is a correct optimization to treat ValidIf as a connection case ValidIf(cond, value, _) => getOrigin(connects)(value) diff --git a/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala b/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala index 10bcadfb..335e1121 100644 --- a/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala +++ b/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala @@ -15,7 +15,7 @@ import collection.mutable /** This pass generates delay reigsters for memories for verilog */ object VerilogMemDelays extends Pass { - val ug = UNKNOWNGENDER + val ug = UnknownFlow type Netlist = collection.mutable.HashMap[String, Expression] implicit def expToString(e: Expression): String = e.serialize private def NOT(e: Expression) = DoPrim(Not, Seq(e), Nil, BoolType) @@ -58,14 +58,14 @@ object VerilogMemDelays extends Pass { // 1) reference to the last pipe register // 2) pipe registers and connects val node = DefNode(NoInfo, namespace.newTemp, netlist(e)) - val wref = WRef(node.name, e.tpe, NodeKind, MALE) + val wref = WRef(node.name, e.tpe, NodeKind, SourceFlow) ((0 until n) foldLeft( (wref, Seq[Statement](node)) )){case ((ex, stmts), i) => val name = namespace newName s"${LowerTypes.loweredName(e)}_pipe_$i" val exx = WRef(name, e.tpe, RegKind, ug) (exx, stmts ++ Seq(DefRegister(NoInfo, name, e.tpe, clk, zero, exx)) ++ (if (i < n - 1 && WrappedExpression.weq(cond, one)) Seq(Connect(NoInfo, exx, ex)) else { val condn = namespace newName s"${LowerTypes.loweredName(e)}_en" - val condx = WRef(condn, BoolType, NodeKind, FEMALE) + val condx = WRef(condn, BoolType, NodeKind, SinkFlow) Seq(DefNode(NoInfo, condn, cond), Connect(NoInfo, exx, Mux(condx, ex, exx, e.tpe))) }) @@ -94,7 +94,7 @@ object VerilogMemDelays extends Pass { Connect(NoInfo, memPortField(mem, writer, "addr"), addr), Connect(NoInfo, memPortField(mem, writer, "data"), data) ) - + stmts ++= ((sx.readers flatMap {reader => // generate latency pipes for read ports (enable & addr) val clk = netlist(memPortField(sx, reader, "clk")) diff --git a/src/main/scala/firrtl/transforms/ConstantPropagation.scala b/src/main/scala/firrtl/transforms/ConstantPropagation.scala index b781f06c..b183e059 100644 --- a/src/main/scala/firrtl/transforms/ConstantPropagation.scala +++ b/src/main/scala/firrtl/transforms/ConstantPropagation.scala @@ -335,9 +335,9 @@ class ConstantPropagation extends Transform with ResolvedAnnotationPaths { val propagated = old match { case p: DoPrim => constPropPrim(p) case m: Mux => constPropMux(m) - case ref @ WRef(rname, _,_, MALE) if nodeMap.contains(rname) => + case ref @ WRef(rname, _,_, SourceFlow) if nodeMap.contains(rname) => constPropNodeRef(ref, nodeMap(rname)) - case ref @ WSubField(WRef(inst, _, InstanceKind, _), pname, _, MALE) => + case ref @ WSubField(WRef(inst, _, InstanceKind, _), pname, _, SourceFlow) => val module = instMap(inst) // Check constSubOutputs to see if the submodule is driving a constant constSubOutputs.get(module).flatMap(_.get(pname)).getOrElse(ref) @@ -407,7 +407,7 @@ class ConstantPropagation extends Transform with ResolvedAnnotationPaths { case ref @ WRef(rname, _,_,_) if swapMap.contains(rname) => ref.copy(name = swapMap(rname)) // Only const prop on the rhs - case ref @ WRef(rname, _,_, MALE) if nodeMap.contains(rname) => + case ref @ WRef(rname, _,_, SourceFlow) if nodeMap.contains(rname) => constPropNodeRef(ref, nodeMap(rname)) case x => x } diff --git a/src/main/scala/firrtl/transforms/DeadCodeElimination.scala b/src/main/scala/firrtl/transforms/DeadCodeElimination.scala index a2f15776..308d68df 100644 --- a/src/main/scala/firrtl/transforms/DeadCodeElimination.scala +++ b/src/main/scala/firrtl/transforms/DeadCodeElimination.scala @@ -108,11 +108,11 @@ class DeadCodeElimination extends Transform with ResolvedAnnotationPaths with Re depGraph.addVertex(LogicNode(mod.name, name)) case mem: DefMemory => // Treat DefMems as a node with outputs depending on the node and node depending on inputs - // From perpsective of the module or instance, MALE expressions are inputs, FEMALE are outputs - val memRef = WRef(mem.name, MemPortUtils.memType(mem), ExpKind, FEMALE) - val exprs = Utils.create_exps(memRef).groupBy(Utils.gender(_)) - val sources = exprs.getOrElse(MALE, List.empty).flatMap(getDeps(_)) - val sinks = exprs.getOrElse(FEMALE, List.empty).flatMap(getDeps(_)) + // From perpsective of the module or instance, SourceFlow expressions are inputs, SinkFlow are outputs + val memRef = WRef(mem.name, MemPortUtils.memType(mem), ExpKind, SinkFlow) + val exprs = Utils.create_exps(memRef).groupBy(Utils.flow(_)) + val sources = exprs.getOrElse(SourceFlow, List.empty).flatMap(getDeps(_)) + val sinks = exprs.getOrElse(SinkFlow, List.empty).flatMap(getDeps(_)) val memNode = getDeps(memRef) match { case Seq(node) => node } depGraph.addVertex(memNode) sinks.foreach(sink => depGraph.addPairWithEdge(sink, memNode)) diff --git a/src/main/scala/firrtl/transforms/Dedup.scala b/src/main/scala/firrtl/transforms/Dedup.scala index cd55a9a4..179ccbe4 100644 --- a/src/main/scala/firrtl/transforms/Dedup.scala +++ b/src/main/scala/firrtl/transforms/Dedup.scala @@ -439,7 +439,7 @@ object DedupModules { def rename(name: String): String = name def retype(name: String)(tpe: Type): Type = { - val exps = Utils.expandRef(WRef(name, tpe, ExpKind, UNKNOWNGENDER)) + val exps = Utils.expandRef(WRef(name, tpe, ExpKind, UnknownFlow)) refs ++= exps.map(Utils.toTarget(main, m.name)) tpe } @@ -465,7 +465,7 @@ object DedupModules { expr.tpe match { case _: GroundType => case b: BundleType => b.fields.foreach { f => onExp(WSubField(expr, f.name, f.tpe)) } - case v: VectorType => (0 until v.size).foreach { i => onExp(WSubIndex(expr, i, v.tpe, UNKNOWNGENDER)) } + case v: VectorType => (0 until v.size).foreach { i => onExp(WSubIndex(expr, i, v.tpe, UnknownFlow)) } } all += expr } diff --git a/src/main/scala/firrtl/transforms/GroupComponents.scala b/src/main/scala/firrtl/transforms/GroupComponents.scala index 70ce37aa..c617e685 100644 --- a/src/main/scala/firrtl/transforms/GroupComponents.scala +++ b/src/main/scala/firrtl/transforms/GroupComponents.scala @@ -213,7 +213,7 @@ class GroupComponents extends firrtl.Transform { added += Connect(NoInfo, WSubField(WRef(label2instance(group)), toPort), otherExp) // Return WRef with new kind (its inside the group Module now) - WRef(toPort, otherExp.tpe, PortKind, MALE) + WRef(toPort, otherExp.tpe, PortKind, SourceFlow) // case 3: source in different group case otherGroup => @@ -227,7 +227,7 @@ class GroupComponents extends firrtl.Transform { added += Connect(NoInfo, WSubField(WRef(groupInst), toPort), WSubField(WRef(otherInst), fromPort)) // Return WRef with new kind (its inside the group Module now) - WRef(toPort, otherExp.tpe, PortKind, MALE) + WRef(toPort, otherExp.tpe, PortKind, SourceFlow) } } diff --git a/src/main/scala/firrtl/transforms/TopWiring.scala b/src/main/scala/firrtl/transforms/TopWiring.scala index e884e02b..65281382 100644 --- a/src/main/scala/firrtl/transforms/TopWiring.scala +++ b/src/main/scala/firrtl/transforms/TopWiring.scala @@ -7,7 +7,7 @@ import firrtl.ir._ import firrtl.passes.{Pass, InferTypes, ResolveKinds, - ResolveGenders, + ResolveFlows, ExpandConnects } import firrtl.annotations._ @@ -227,11 +227,11 @@ class TopWiringTransform extends Transform { val passes = Seq( InferTypes, ResolveKinds, - ResolveGenders, + ResolveFlows, ExpandConnects, InferTypes, ResolveKinds, - ResolveGenders + ResolveFlows ) passes.foldLeft(circuit) { case (c: Circuit, p: Pass) => p.run(c) } } diff --git a/src/main/scala/tutorial/lesson2-working-ir/AnalyzeCircuit.scala b/src/main/scala/tutorial/lesson2-working-ir/AnalyzeCircuit.scala index e7a53ec5..87cc3c59 100644 --- a/src/main/scala/tutorial/lesson2-working-ir/AnalyzeCircuit.scala +++ b/src/main/scala/tutorial/lesson2-working-ir/AnalyzeCircuit.scala @@ -82,7 +82,7 @@ class Ledger { * creating new WIR nodes, use the following "unknown" values in the WIR node, and then call [[firrtl.ResolveAndCheck]] * at the end of your transform: * - Kind -> ExpKind - * - Gender -> UNKNOWNGENDER + * - Flow -> UnknownFlow * - Type -> UnknownType * * The following [[firrtl.CircuitForm]]s require WIR instead of IR nodes: diff --git a/src/test/scala/firrtlTests/CheckInitializationSpec.scala b/src/test/scala/firrtlTests/CheckInitializationSpec.scala index 9b1f3a9c..3af63c6e 100644 --- a/src/test/scala/firrtlTests/CheckInitializationSpec.scala +++ b/src/test/scala/firrtlTests/CheckInitializationSpec.scala @@ -16,8 +16,8 @@ class CheckInitializationSpec extends FirrtlFlatSpec { ResolveKinds, InferTypes, CheckTypes, - ResolveGenders, - CheckGenders, + ResolveFlows, + CheckFlows, new InferWidths, CheckWidths, PullMuxes, diff --git a/src/test/scala/firrtlTests/CheckSpec.scala b/src/test/scala/firrtlTests/CheckSpec.scala index 54dc60ab..96275003 100644 --- a/src/test/scala/firrtlTests/CheckSpec.scala +++ b/src/test/scala/firrtlTests/CheckSpec.scala @@ -5,7 +5,7 @@ package firrtlTests import org.scalatest._ import firrtl.{Parser, CircuitState, UnknownForm, Transform} import firrtl.ir.Circuit -import firrtl.passes.{Pass,ToWorkingIR,CheckHighForm,ResolveKinds,InferTypes,CheckTypes,PassException,InferWidths,CheckWidths,ResolveGenders,CheckGenders} +import firrtl.passes.{Pass,ToWorkingIR,CheckHighForm,ResolveKinds,InferTypes,CheckTypes,PassException,InferWidths,CheckWidths,ResolveFlows,CheckFlows} class CheckSpec extends FlatSpec with Matchers { val defaultPasses = Seq(ToWorkingIR, CheckHighForm) @@ -176,8 +176,8 @@ class CheckSpec extends FlatSpec with Matchers { ResolveKinds, InferTypes, CheckTypes, - ResolveGenders, - CheckGenders, + ResolveFlows, + CheckFlows, new InferWidths, CheckWidths) val input = diff --git a/src/test/scala/firrtlTests/ChirrtlSpec.scala b/src/test/scala/firrtlTests/ChirrtlSpec.scala index aeb70c8d..fba81ec7 100644 --- a/src/test/scala/firrtlTests/ChirrtlSpec.scala +++ b/src/test/scala/firrtlTests/ChirrtlSpec.scala @@ -16,8 +16,8 @@ class ChirrtlSpec extends FirrtlFlatSpec { ResolveKinds, InferTypes, CheckTypes, - ResolveGenders, - CheckGenders, + ResolveFlows, + CheckFlows, new InferWidths, CheckWidths, PullMuxes, diff --git a/src/test/scala/firrtlTests/ClockListTests.scala b/src/test/scala/firrtlTests/ClockListTests.scala index dde719d5..a30416b3 100644 --- a/src/test/scala/firrtlTests/ClockListTests.scala +++ b/src/test/scala/firrtlTests/ClockListTests.scala @@ -24,7 +24,7 @@ class ClockListTests extends FirrtlFlatSpec { ToWorkingIR, ResolveKinds, InferTypes, - ResolveGenders, + ResolveFlows, new InferWidths ) diff --git a/src/test/scala/firrtlTests/ConstantPropagationTests.scala b/src/test/scala/firrtlTests/ConstantPropagationTests.scala index da3e9b41..79e73c80 100644 --- a/src/test/scala/firrtlTests/ConstantPropagationTests.scala +++ b/src/test/scala/firrtlTests/ConstantPropagationTests.scala @@ -13,7 +13,7 @@ class ConstantPropagationSpec extends FirrtlFlatSpec { ToWorkingIR, ResolveKinds, InferTypes, - ResolveGenders, + ResolveFlows, new InferWidths, new ConstantPropagation) protected def exec(input: String) = { diff --git a/src/test/scala/firrtlTests/ExpandWhensSpec.scala b/src/test/scala/firrtlTests/ExpandWhensSpec.scala index a1ac8a31..af82cc38 100644 --- a/src/test/scala/firrtlTests/ExpandWhensSpec.scala +++ b/src/test/scala/firrtlTests/ExpandWhensSpec.scala @@ -20,8 +20,8 @@ class ExpandWhensSpec extends FirrtlFlatSpec { Uniquify, ResolveKinds, InferTypes, - ResolveGenders, - CheckGenders, + ResolveFlows, + CheckFlows, new InferWidths, CheckWidths, PullMuxes, @@ -141,4 +141,3 @@ class ExpandWhensSpec extends FirrtlFlatSpec { } class ExpandWhensExecutionTest extends ExecutionTest("ExpandWhens", "/passes/ExpandWhens") - diff --git a/src/test/scala/firrtlTests/LowerTypesSpec.scala b/src/test/scala/firrtlTests/LowerTypesSpec.scala index 30ef795b..be9d738b 100644 --- a/src/test/scala/firrtlTests/LowerTypesSpec.scala +++ b/src/test/scala/firrtlTests/LowerTypesSpec.scala @@ -18,8 +18,8 @@ class LowerTypesSpec extends FirrtlFlatSpec { ResolveKinds, InferTypes, CheckTypes, - ResolveGenders, - CheckGenders, + ResolveFlows, + CheckFlows, new InferWidths, CheckWidths, PullMuxes, @@ -31,7 +31,7 @@ class LowerTypesSpec extends FirrtlFlatSpec { new ConstantPropagation, ResolveKinds, InferTypes, - ResolveGenders, + ResolveFlows, new InferWidths, LowerTypes) diff --git a/src/test/scala/firrtlTests/ReplaceAccessesSpec.scala b/src/test/scala/firrtlTests/ReplaceAccessesSpec.scala index 64977c7f..e9ef3bcd 100644 --- a/src/test/scala/firrtlTests/ReplaceAccessesSpec.scala +++ b/src/test/scala/firrtlTests/ReplaceAccessesSpec.scala @@ -13,7 +13,7 @@ class ReplaceAccessesSpec extends FirrtlFlatSpec { ToWorkingIR, ResolveKinds, InferTypes, - ResolveGenders, + ResolveFlows, new InferWidths, ReplaceAccesses) protected def exec(input: String) = { diff --git a/src/test/scala/firrtlTests/UnitTests.scala b/src/test/scala/firrtlTests/UnitTests.scala index 0ef4f709..b7df945f 100644 --- a/src/test/scala/firrtlTests/UnitTests.scala +++ b/src/test/scala/firrtlTests/UnitTests.scala @@ -95,7 +95,7 @@ class UnitTests extends FirrtlFlatSpec { ResolveKinds, InferTypes, CheckTypes, - ResolveGenders, + ResolveFlows, ExpandConnects) val input = """circuit Unit : @@ -157,7 +157,7 @@ class UnitTests extends FirrtlFlatSpec { ToWorkingIR, ResolveKinds, InferTypes, - ResolveGenders, + ResolveFlows, new InferWidths, SplitExpressions ) @@ -181,7 +181,7 @@ class UnitTests extends FirrtlFlatSpec { ToWorkingIR, ResolveKinds, InferTypes, - ResolveGenders, + ResolveFlows, new InferWidths, PadWidths ) @@ -202,7 +202,7 @@ class UnitTests extends FirrtlFlatSpec { ToWorkingIR, ResolveKinds, InferTypes, - ResolveGenders, + ResolveFlows, new InferWidths, PullMuxes, ExpandConnects, @@ -210,8 +210,8 @@ class UnitTests extends FirrtlFlatSpec { new ConstantPropagation ) val input = - """circuit AssignViaDeref : - | module AssignViaDeref : + """circuit AssignViaDeref : + | module AssignViaDeref : | input clock : Clock | input reset : UInt<1> | output io : {a : UInt<8>, sel : UInt<1>} @@ -242,7 +242,7 @@ class UnitTests extends FirrtlFlatSpec { ToWorkingIR, ResolveKinds, InferTypes, - ResolveGenders, + ResolveFlows, new InferWidths, CheckWidths) val input = @@ -261,7 +261,7 @@ class UnitTests extends FirrtlFlatSpec { ToWorkingIR, ResolveKinds, InferTypes, - ResolveGenders, + ResolveFlows, new InferWidths, CheckWidths) val input = @@ -280,7 +280,7 @@ class UnitTests extends FirrtlFlatSpec { ToWorkingIR, ResolveKinds, InferTypes, - ResolveGenders, + ResolveFlows, new InferWidths, CheckWidths) val input = @@ -388,12 +388,12 @@ class UnitTests extends FirrtlFlatSpec { ToWorkingIR, ResolveKinds, InferTypes, - ResolveGenders, + ResolveFlows, new InferWidths, PullMuxes, ExpandConnects, RemoveAccesses, - ResolveGenders, + ResolveFlows, new ConstantPropagation ) val input = @@ -412,13 +412,13 @@ class UnitTests extends FirrtlFlatSpec { val ut2 = UIntType(IntWidth(BigInt(2))) val ut1 = UIntType(IntWidth(BigInt(1))) - val mgen = WRef("_array_index", ut16, WireKind, MALE) - val fgen = WRef("_array_index", ut16, WireKind, FEMALE) - val index = WRef("index", ut2, PortKind, MALE) - val out = WRef("out", ut16, PortKind, FEMALE) + val mgen = WRef("_array_index", ut16, WireKind, SourceFlow) + val fgen = WRef("_array_index", ut16, WireKind, SinkFlow) + val index = WRef("index", ut2, PortKind, SourceFlow) + val out = WRef("out", ut16, PortKind, SinkFlow) def eq(e1: Expression, e2: Expression): Expression = DoPrim(PrimOps.Eq, Seq(e1, e2), Nil, ut1) - def array(v: Int): Expression = WSubIndex(WRef("array", VectorType(ut16, 3), WireKind, MALE), v, ut16, MALE) + def array(v: Int): Expression = WSubIndex(WRef("array", VectorType(ut16, 3), WireKind, SourceFlow), v, ut16, SourceFlow) result should containTree { case DefWire(_, "_array_index", `ut16`) => true } result should containTree { case IsInvalid(_, `fgen`) => true } diff --git a/src/test/scala/firrtlTests/WidthSpec.scala b/src/test/scala/firrtlTests/WidthSpec.scala index 96bd249c..4c0e7f70 100644 --- a/src/test/scala/firrtlTests/WidthSpec.scala +++ b/src/test/scala/firrtlTests/WidthSpec.scala @@ -53,7 +53,7 @@ class WidthSpec extends FirrtlFlatSpec { ResolveKinds, InferTypes, CheckTypes, - ResolveGenders, + ResolveFlows, new InferWidths, CheckWidths) val input = @@ -76,7 +76,7 @@ class WidthSpec extends FirrtlFlatSpec { ResolveKinds, InferTypes, CheckTypes, - ResolveGenders, + ResolveFlows, new InferWidths, CheckWidths) val input = @@ -95,7 +95,7 @@ class WidthSpec extends FirrtlFlatSpec { ResolveKinds, InferTypes, CheckTypes, - ResolveGenders, + ResolveFlows, new InferWidths, CheckWidths) val input = @@ -120,7 +120,7 @@ class WidthSpec extends FirrtlFlatSpec { ResolveKinds, InferTypes, CheckTypes, - ResolveGenders, + ResolveFlows, new InferWidths) val input = """circuit Unit : @@ -142,7 +142,7 @@ class WidthSpec extends FirrtlFlatSpec { ResolveKinds, InferTypes, CheckTypes, - ResolveGenders, + ResolveFlows, new InferWidths) val input = """circuit Unit : @@ -165,7 +165,7 @@ class WidthSpec extends FirrtlFlatSpec { ResolveKinds, InferTypes, CheckTypes, - ResolveGenders, + ResolveFlows, new InferWidths, CheckWidths) val input = diff --git a/src/test/scala/firrtlTests/WiringTests.scala b/src/test/scala/firrtlTests/WiringTests.scala index 4fe4a46c..ec69c39f 100644 --- a/src/test/scala/firrtlTests/WiringTests.scala +++ b/src/test/scala/firrtlTests/WiringTests.scala @@ -33,7 +33,7 @@ class WiringTests extends FirrtlFlatSpec { ToWorkingIR, ResolveKinds, InferTypes, - ResolveGenders, + ResolveFlows, new InferWidths ) diff --git a/src/test/scala/firrtlTests/ZeroWidthTests.scala b/src/test/scala/firrtlTests/ZeroWidthTests.scala index eb955f29..eb3d1a96 100644 --- a/src/test/scala/firrtlTests/ZeroWidthTests.scala +++ b/src/test/scala/firrtlTests/ZeroWidthTests.scala @@ -15,7 +15,7 @@ class ZeroWidthTests extends FirrtlFlatSpec { ToWorkingIR, ResolveKinds, InferTypes, - ResolveGenders, + ResolveFlows, new InferWidths, ZeroWidth) private def exec (input: String) = { @@ -218,12 +218,12 @@ class ZeroWidthVerilog extends FirrtlFlatSpec { "Circuit" should "accept zero width wires" in { val compiler = new VerilogCompiler val input = - """circuit Top : - | module Top : + """circuit Top : + | module Top : | input y: UInt<0> | output x: UInt<3> | x <= y""".stripMargin - val check = + val check = """module Top( | output [2:0] x |); diff --git a/src/test/scala/firrtlTests/fixed/FixedTypeInferenceSpec.scala b/src/test/scala/firrtlTests/fixed/FixedTypeInferenceSpec.scala index 667db7b0..6bf86479 100644 --- a/src/test/scala/firrtlTests/fixed/FixedTypeInferenceSpec.scala +++ b/src/test/scala/firrtlTests/fixed/FixedTypeInferenceSpec.scala @@ -28,8 +28,8 @@ class FixedTypeInferenceSpec extends FirrtlFlatSpec { ResolveKinds, InferTypes, CheckTypes, - ResolveGenders, - CheckGenders, + ResolveFlows, + CheckFlows, new InferWidths, CheckWidths) val input = @@ -58,8 +58,8 @@ class FixedTypeInferenceSpec extends FirrtlFlatSpec { ResolveKinds, InferTypes, CheckTypes, - ResolveGenders, - CheckGenders, + ResolveFlows, + CheckFlows, new InferWidths, CheckWidths) val input = @@ -84,8 +84,8 @@ class FixedTypeInferenceSpec extends FirrtlFlatSpec { ResolveKinds, InferTypes, CheckTypes, - ResolveGenders, - CheckGenders, + ResolveFlows, + CheckFlows, new InferWidths, CheckWidths) val input = @@ -110,8 +110,8 @@ class FixedTypeInferenceSpec extends FirrtlFlatSpec { ResolveKinds, InferTypes, CheckTypes, - ResolveGenders, - CheckGenders, + ResolveFlows, + CheckFlows, new InferWidths, CheckWidths) val input = @@ -136,8 +136,8 @@ class FixedTypeInferenceSpec extends FirrtlFlatSpec { ResolveKinds, InferTypes, CheckTypes, - ResolveGenders, - CheckGenders, + ResolveFlows, + CheckFlows, new InferWidths, CheckWidths) val input = @@ -162,8 +162,8 @@ class FixedTypeInferenceSpec extends FirrtlFlatSpec { ResolveKinds, InferTypes, CheckTypes, - ResolveGenders, - CheckGenders, + ResolveFlows, + CheckFlows, new InferWidths, CheckWidths) val input = @@ -188,8 +188,8 @@ class FixedTypeInferenceSpec extends FirrtlFlatSpec { ResolveKinds, InferTypes, CheckTypes, - ResolveGenders, - CheckGenders, + ResolveFlows, + CheckFlows, new InferWidths, CheckWidths) val input = @@ -228,8 +228,8 @@ class FixedTypeInferenceSpec extends FirrtlFlatSpec { ResolveKinds, InferTypes, CheckTypes, - ResolveGenders, - CheckGenders, + ResolveFlows, + CheckFlows, new InferWidths, CheckWidths) val input = @@ -254,8 +254,8 @@ class FixedTypeInferenceSpec extends FirrtlFlatSpec { ResolveKinds, InferTypes, CheckTypes, - ResolveGenders, - CheckGenders, + ResolveFlows, + CheckFlows, new InferWidths, CheckWidths, ConvertFixedToSInt) @@ -334,4 +334,3 @@ class FixedTypeInferenceSpec extends FirrtlFlatSpec { executeTest(input("cmem"), check(0, 1, 1).split("\n") map normalized, new LowFirrtlCompiler) } } - diff --git a/src/test/scala/firrtlTests/fixed/RemoveFixedTypeSpec.scala b/src/test/scala/firrtlTests/fixed/RemoveFixedTypeSpec.scala index 21a39e83..8686bd0f 100644 --- a/src/test/scala/firrtlTests/fixed/RemoveFixedTypeSpec.scala +++ b/src/test/scala/firrtlTests/fixed/RemoveFixedTypeSpec.scala @@ -28,8 +28,8 @@ class RemoveFixedTypeSpec extends FirrtlFlatSpec { ResolveKinds, InferTypes, CheckTypes, - ResolveGenders, - CheckGenders, + ResolveFlows, + CheckFlows, new InferWidths, CheckWidths, ConvertFixedToSInt) @@ -58,8 +58,8 @@ class RemoveFixedTypeSpec extends FirrtlFlatSpec { ResolveKinds, InferTypes, CheckTypes, - ResolveGenders, - CheckGenders, + ResolveFlows, + CheckFlows, new InferWidths, CheckWidths, ConvertFixedToSInt) @@ -89,8 +89,8 @@ class RemoveFixedTypeSpec extends FirrtlFlatSpec { ResolveKinds, InferTypes, CheckTypes, - ResolveGenders, - CheckGenders, + ResolveFlows, + CheckFlows, new InferWidths, CheckWidths, ConvertFixedToSInt) @@ -116,8 +116,8 @@ class RemoveFixedTypeSpec extends FirrtlFlatSpec { ResolveKinds, InferTypes, CheckTypes, - ResolveGenders, - CheckGenders, + ResolveFlows, + CheckFlows, new InferWidths, CheckWidths, ConvertFixedToSInt) @@ -143,8 +143,8 @@ class RemoveFixedTypeSpec extends FirrtlFlatSpec { ResolveKinds, InferTypes, CheckTypes, - ResolveGenders, - CheckGenders, + ResolveFlows, + CheckFlows, new InferWidths, CheckWidths, ConvertFixedToSInt) @@ -195,8 +195,8 @@ class RemoveFixedTypeSpec extends FirrtlFlatSpec { ResolveKinds, InferTypes, CheckTypes, - ResolveGenders, - CheckGenders, + ResolveFlows, + CheckFlows, new InferWidths, CheckWidths, ConvertFixedToSInt) @@ -215,4 +215,3 @@ class RemoveFixedTypeSpec extends FirrtlFlatSpec { executeTest(input, check.split("\n") map normalized, passes) } } - diff --git a/src/test/scala/firrtlTests/transforms/InferWidthsWithAnnosSpec.scala b/src/test/scala/firrtlTests/transforms/InferWidthsWithAnnosSpec.scala index 54a3df40..46fb310a 100644 --- a/src/test/scala/firrtlTests/transforms/InferWidthsWithAnnosSpec.scala +++ b/src/test/scala/firrtlTests/transforms/InferWidthsWithAnnosSpec.scala @@ -35,7 +35,7 @@ class InferWidthsWithAnnosSpec extends FirrtlFlatSpec { ResolveKinds, InferTypes, CheckTypes, - ResolveGenders, + ResolveFlows, new InferWidths, CheckWidths) @@ -64,7 +64,7 @@ class InferWidthsWithAnnosSpec extends FirrtlFlatSpec { ResolveKinds, InferTypes, CheckTypes, - ResolveGenders, + ResolveFlows, new InferWidths, CheckWidths) @@ -107,7 +107,7 @@ class InferWidthsWithAnnosSpec extends FirrtlFlatSpec { ResolveKinds, InferTypes, CheckTypes, - ResolveGenders, + ResolveFlows, new InferWidths, CheckWidths) @@ -156,7 +156,7 @@ class InferWidthsWithAnnosSpec extends FirrtlFlatSpec { ToWorkingIR, ResolveKinds, InferTypes, - ResolveGenders, + ResolveFlows, new InferWidths, CheckWidths, new WiringTransform, |