add test case for clock type connection (#239)

1 files changed, 42 insertions, 1 deletions

diff --git a/src/test/scala/firrtlTests/CheckSpec.scala b/src/test/scala/firrtlTests/CheckSpec.scala
index 65873540..8acbd9fb 100644
--- a/src/test/scala/firrtlTests/CheckSpec.scala
+++ b/src/test/scala/firrtlTests/CheckSpec.scala
@@ -5,7 +5,7 @@ import org.scalatest._
 import org.scalatest.prop._
 import firrtl.Parser
 import firrtl.ir.Circuit
-import firrtl.passes.{Pass,ToWorkingIR,CheckHighForm,ResolveKinds,InferTypes,CheckTypes,PassExceptions}
+import firrtl.passes.{Pass,ToWorkingIR,CheckHighForm,ResolveKinds,InferTypes,CheckTypes,PassExceptions,InferWidths,CheckWidths,ResolveGenders,CheckGenders}
 
 class CheckSpec extends FlatSpec with Matchers {
   "Connecting bundles of different types" should "throw an exception" in {
@@ -142,4 +142,45 @@ class CheckSpec extends FlatSpec with Matchers {
 
   }
 
+  "Clock Types" should "be connectable" in {
+    val passes = Seq(
+      ToWorkingIR,
+      CheckHighForm,
+      ResolveKinds,
+      InferTypes,
+      CheckTypes,
+      ResolveGenders,
+      CheckGenders,
+      InferWidths,
+      CheckWidths)
+    val input =
+      """
+          |circuit TheRealTop : 
+          |    
+          |  module Top : 
+          |    output io : {flip debug_clk : Clock}
+          |        
+          |  extmodule BlackBoxTop : 
+          |    input jtag : {TCK : Clock}
+          | 
+          |  module TheRealTop : 
+          |    input clk : Clock
+          |    input reset : UInt<1>
+          |    output io : {flip jtag : {TCK : Clock}}
+          |    
+          |    io is invalid
+          |    inst sub of Top
+          |    sub.io is invalid
+          |    inst bb of BlackBoxTop
+          |    bb.jtag is invalid
+          |    bb.jtag <- io.jtag 
+          | 
+          |    sub.io.debug_clk <= io.jtag.TCK 
+          |
+          |""".stripMargin
+    passes.foldLeft(Parser.parse(input.split("\n").toIterator)) {
+      (c: Circuit, p: Pass) => p.run(c)
+    }
+  }
+
 }