Merge pull request #1753 from freechipsproject/rm-duplicate-tests

Remove overlapping inputForm=LowForm tests

2 files changed, 21 insertions, 69 deletions

diff --git a/src/test/scala/firrtlTests/CustomTransformSpec.scala b/src/test/scala/firrtlTests/CustomTransformSpec.scala
index 7a683ea9..9141a9f7 100644
--- a/src/test/scala/firrtlTests/CustomTransformSpec.scala
+++ b/src/test/scala/firrtlTests/CustomTransformSpec.scala
@@ -6,11 +6,11 @@ import firrtl.ir.Circuit
 import firrtl._
 import firrtl.passes.Pass
 import firrtl.ir._
-import firrtl.stage.{FirrtlSourceAnnotation, FirrtlStage, Forms, RunFirrtlTransformAnnotation}
+import firrtl.stage.{FirrtlSourceAnnotation, FirrtlStage, RunFirrtlTransformAnnotation}
 import firrtl.options.Dependency
 import firrtl.transforms.{IdentityTransform, LegalizeAndReductionsTransform}
 import firrtl.testutils._
-import firrtl.transforms.formal.{RemoveVerificationStatements, ConvertAsserts}
+import firrtl.transforms.formal.ConvertAsserts
 
 import scala.reflect.runtime
 
@@ -150,40 +150,29 @@ class CustomTransformSpec extends FirrtlFlatSpec {
 
   they should "run right before the emitter* when inputForm=LowForm" in {
 
-    val custom = Dependency[IdentityLowForm]
-
-    def testOrder(after: Seq[Dependency[Transform]], before: Seq[Dependency[Transform]]): Unit = {
-      val expectedSlice: Seq[Dependency[Transform]] = before ++: custom +: after
-
-      info(expectedSlice.map(_.getSimpleName).mkString(" -> ") + " ok!")
-
-      val compiler = new firrtl.stage.transforms.Compiler(custom +: after)
-      info("Transform Order: \n" + compiler.prettyPrint("    "))
-
+    val locationMap = Map(
+      Dependency[LowFirrtlEmitter]      -> Dependency[LowFirrtlEmitter],
+      Dependency[MinimumVerilogEmitter] -> Dependency(ConvertAsserts),
+      Dependency[VerilogEmitter]        -> Dependency(ConvertAsserts),
+      Dependency[SystemVerilogEmitter]  -> Dependency[LegalizeAndReductionsTransform]
+    )
 
-      compiler
+    Seq(
+      Dependency[LowFirrtlEmitter],
+      Dependency[MinimumVerilogEmitter],
+      Dependency[VerilogEmitter],
+      Dependency[SystemVerilogEmitter]
+    ).foreach { emitter =>
+      val custom = Dependency[IdentityLowForm]
+      val tm = new firrtl.stage.transforms.Compiler(custom :: emitter :: Nil)
+      info(s"when using ${emitter.getObject.name}")
+      tm
         .flattenedTransformOrder
-        .map(Dependency.fromTransform(_))
-        .containsSlice(expectedSlice) should be (true)
+        .map(Dependency.fromTransform)
+        .sliding(2)
+        .toList should contain (Seq(custom, locationMap(emitter)))
     }
 
-    val Seq(low, lowMinOpt, lowOpt) =
-      Seq(Forms.LowForm, Forms.LowFormMinimumOptimized, Forms.LowFormOptimized)
-        .map(target => new firrtl.stage.transforms.Compiler(target))
-        .map(_.flattenedTransformOrder.map(Dependency.fromTransform(_)))
-
-    Seq( (Seq(Dependency[LowFirrtlEmitter]),             Seq(low.last)      ),
-         (Seq(Dependency[LegalizeAndReductionsTransform],
-           Dependency(ConvertAsserts),
-           Dependency[RemoveVerificationStatements],
-           Dependency[MinimumVerilogEmitter]),           Seq(lowMinOpt.last)),
-         (Seq(Dependency[LegalizeAndReductionsTransform],
-           Dependency(ConvertAsserts),
-           Dependency[RemoveVerificationStatements],
-           Dependency[VerilogEmitter]),                  Seq(lowOpt.last)    ),
-         (Seq(Dependency[LegalizeAndReductionsTransform],
-           Dependency[SystemVerilogEmitter]),            Seq(lowOpt.last)   )
-    ).foreach((testOrder _).tupled)
   }
 
   they should "work if placed inside an object" in {
diff --git a/src/test/scala/firrtlTests/LoweringCompilersSpec.scala b/src/test/scala/firrtlTests/LoweringCompilersSpec.scala
index 82750fdf..7df621d3 100644
--- a/src/test/scala/firrtlTests/LoweringCompilersSpec.scala
+++ b/src/test/scala/firrtlTests/LoweringCompilersSpec.scala
@@ -8,7 +8,6 @@ import firrtl._
 import firrtl.passes
 import firrtl.options.Dependency
 import firrtl.stage.{Forms, TransformManager}
-import firrtl.transforms.IdentityTransform
 
 sealed trait PatchAction { val line: Int }
 
@@ -339,40 +338,4 @@ class LoweringCompilersSpec extends FlatSpec with Matchers {
     compare(expected, tm)
   }
 
-  it should "schedule inputForm=LowForm after MiddleFirrtlToLowFirrtl for the LowFirrtlEmitter" in {
-    val expected =
-      new TransformManager(Forms.LowForm).flattenedTransformOrder ++
-        Seq(new Transforms.LowToLow, new firrtl.LowFirrtlEmitter)
-    val tm = (new TransformManager(Seq(Dependency[firrtl.LowFirrtlEmitter], Dependency[Transforms.LowToLow])))
-    compare(expected, tm)
-  }
-
-  it should "schedule inputForm=LowForm after MinimumLowFirrtlOptimizations for the MinimalVerilogEmitter" in {
-    val expected =
-      new TransformManager(Forms.LowFormMinimumOptimized).flattenedTransformOrder ++
-        Seq(new Transforms.LowToLow, new firrtl.MinimumVerilogEmitter)
-    val tm = (new TransformManager(Seq(Dependency[firrtl.MinimumVerilogEmitter], Dependency[Transforms.LowToLow])))
-    val patches = Seq(
-      Add(63, Seq(
-        Dependency(firrtl.transforms.formal.ConvertAsserts),
-        Dependency[firrtl.transforms.formal.RemoveVerificationStatements],
-        Dependency[firrtl.transforms.LegalizeAndReductionsTransform]))
-    )
-    compare(expected, tm, patches)
-  }
-
-  it should "schedule inputForm=LowForm after LowFirrtlOptimizations for the VerilogEmitter" in {
-    val expected =
-      new TransformManager(Forms.LowFormOptimized).flattenedTransformOrder ++
-        Seq(new Transforms.LowToLow, new firrtl.VerilogEmitter)
-    val tm = (new TransformManager(Seq(Dependency[firrtl.VerilogEmitter], Dependency[Transforms.LowToLow])))
-    val patches = Seq(
-      Add(70, Seq(
-        Dependency(firrtl.transforms.formal.ConvertAsserts),
-        Dependency[firrtl.transforms.formal.RemoveVerificationStatements],
-        Dependency[firrtl.transforms.LegalizeAndReductionsTransform]))
-    )
-    compare(expected, tm, patches)
-  }
-
 }