diff options
| author | Donggyu Kim | 2016-09-07 14:58:15 -0700 |
|---|---|---|
| committer | Donggyu Kim | 2016-09-07 16:34:31 -0700 |
| commit | c532c27b81b278cc530ec69e39731b9b98bc294b (patch) | |
| tree | 46e89eaaa734bc41b169b9a594d678d2da6c5415 /src | |
| parent | db584ed4cb31731e1561e447d5b3609f234fc8db (diff) | |
clean up miscs
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/scala/firrtl/PrimOps.scala | 6 | ||||
| -rw-r--r-- | src/main/scala/firrtl/Utils.scala | 3 | ||||
| -rw-r--r-- | src/main/scala/firrtl/passes/ConstProp.scala | 2 | ||||
| -rw-r--r-- | src/main/scala/firrtl/passes/Inline.scala | 6 | ||||
| -rw-r--r-- | src/main/scala/firrtl/passes/RemoveEmpty.scala | 2 | ||||
| -rw-r--r-- | src/main/scala/firrtl/passes/ReplaceSubAccess.scala | 7 |
6 files changed, 9 insertions, 17 deletions
diff --git a/src/main/scala/firrtl/PrimOps.scala b/src/main/scala/firrtl/PrimOps.scala index 8b705b29..60c2082a 100644 --- a/src/main/scala/firrtl/PrimOps.scala +++ b/src/main/scala/firrtl/PrimOps.scala @@ -138,9 +138,9 @@ object PrimOps extends LazyLogging { def t1 () = a(0).tpe def t2 () = a(1).tpe def t3 () = a(2).tpe - def w1 () = Utils.widthBANG(a(0).tpe) - def w2 () = Utils.widthBANG(a(1).tpe) - def w3 () = Utils.widthBANG(a(2).tpe) + def w1 () = Utils.width_BANG(a(0).tpe) + def w2 () = Utils.width_BANG(a(1).tpe) + def w3 () = Utils.width_BANG(a(2).tpe) def c1 () = IntWidth(c(0)) def c2 () = IntWidth(c(1)) o match { diff --git a/src/main/scala/firrtl/Utils.scala b/src/main/scala/firrtl/Utils.scala index 9404e5e2..ea8ff4b7 100644 --- a/src/main/scala/firrtl/Utils.scala +++ b/src/main/scala/firrtl/Utils.scala @@ -239,10 +239,11 @@ object Utils extends LazyLogging { } ////===================================== - def widthBANG (t:Type) : Width = t match { + def width_BANG(t: Type) : Width = t match { case g: GroundType => g.width case t => error("No width!") } + def width_BANG(e: Expression) : Width = width_BANG(e.tpe) def long_BANG(t: Type): Long = t match { case (g: GroundType) => g.width match { case IntWidth(x) => x.toLong diff --git a/src/main/scala/firrtl/passes/ConstProp.scala b/src/main/scala/firrtl/passes/ConstProp.scala index 2e8b53f3..a4d9078c 100644 --- a/src/main/scala/firrtl/passes/ConstProp.scala +++ b/src/main/scala/firrtl/passes/ConstProp.scala @@ -234,7 +234,7 @@ object ConstProp extends Pass { val hi = e.consts(0).toInt val lo = e.consts(1).toInt require(hi >= lo) - UIntLiteral((lit.value >> lo) & ((BigInt(1) << (hi - lo + 1)) - 1), widthBANG(e.tpe)) + UIntLiteral((lit.value >> lo) & ((BigInt(1) << (hi - lo + 1)) - 1), width_BANG(e.tpe)) } case x if long_BANG(e.tpe) == long_BANG(x.tpe) => x.tpe match { case t: UIntType => x diff --git a/src/main/scala/firrtl/passes/Inline.scala b/src/main/scala/firrtl/passes/Inline.scala index a8fda1bf..c4529bd9 100644 --- a/src/main/scala/firrtl/passes/Inline.scala +++ b/src/main/scala/firrtl/passes/Inline.scala @@ -4,11 +4,9 @@ package passes // Datastructures import scala.collection.mutable -import firrtl.Mappers.{ExpMap,StmtMap} import firrtl.ir._ -import firrtl.passes.{PassException,PassExceptions} -import Annotations.{Loose, Unstable, Annotation, TransID, Named, ModuleName, ComponentName, CircuitName, AnnotationMap} - +import firrtl.Annotations._ +import firrtl.Mappers.{ExpMap, StmtMap} // Tags an annotation to be consumed by this pass case class InlineAnnotation(target: Named, tID: TransID) extends Annotation with Loose with Unstable { diff --git a/src/main/scala/firrtl/passes/RemoveEmpty.scala b/src/main/scala/firrtl/passes/RemoveEmpty.scala index e765d1f4..7ba2ef09 100644 --- a/src/main/scala/firrtl/passes/RemoveEmpty.scala +++ b/src/main/scala/firrtl/passes/RemoveEmpty.scala @@ -15,5 +15,3 @@ object RemoveEmpty extends Pass { } def run(c: Circuit): Circuit = Circuit(c.info, c.modules.map(onModule _), c.main) } - -// vim: set ts=4 sw=4 et: diff --git a/src/main/scala/firrtl/passes/ReplaceSubAccess.scala b/src/main/scala/firrtl/passes/ReplaceSubAccess.scala index 8e911a96..ce95be13 100644 --- a/src/main/scala/firrtl/passes/ReplaceSubAccess.scala +++ b/src/main/scala/firrtl/passes/ReplaceSubAccess.scala @@ -22,11 +22,6 @@ object ReplaceAccesses extends Pass { case e => e map onExp } - val newModules = c.modules map { - case m: ExtModule => m - case Module(i, n, ps, b) => Module(i, n, ps, onStmt(b)) - } - - Circuit(c.info, newModules, c.main) + c copy (modules = c.modules map (_ map onStmt)) } } |
