Changed wmask to convert from VecType to UInt

* Instead of filling the whole data width
* Added helper functions in MemUtils

2 files changed, 47 insertions, 9 deletions

diff --git a/src/main/scala/firrtl/passes/MemUtils.scala b/src/main/scala/firrtl/passes/MemUtils.scala
index 4714f354..c606208c 100644
--- a/src/main/scala/firrtl/passes/MemUtils.scala
+++ b/src/main/scala/firrtl/passes/MemUtils.scala
@@ -135,6 +135,8 @@ object MemPortUtils {
 
   import AnalysisUtils._
 
+  def flattenType(t: Type) = UIntType(IntWidth(bitWidth(t)))
+
   def defaultPortSeq(mem: DefMemory) = Seq(
     Field("addr", Default, UIntType(IntWidth(ceil_log2(mem.depth)))),
     Field("en", Default, UIntType(IntWidth(1))),
@@ -142,6 +144,7 @@ object MemPortUtils {
   )
 
   def rPortToBundle(mem: DefMemory) = BundleType(defaultPortSeq(mem) :+ Field("data", Flip, mem.dataType))
+  def rPortToFlattenBundle(mem: DefMemory) = BundleType(defaultPortSeq(mem) :+ Field("data", Flip, flattenType(mem.dataType)))
 
   def wPortToBundle(mem: DefMemory) = {
     val defaultSeq = defaultPortSeq(mem) :+ Field("data", Default, mem.dataType)
@@ -150,6 +153,13 @@ object MemPortUtils {
       else defaultSeq
     )
   }
+  def wPortToFlattenBundle(mem: DefMemory) = {
+    val defaultSeq = defaultPortSeq(mem) :+ Field("data", Default, flattenType(mem.dataType))
+    BundleType(
+      if (containsInfo(mem.info,"maskGran")) defaultSeq :+ Field("mask", Default, flattenType(create_mask(mem.dataType)))
+      else defaultSeq
+    )  
+  }
 
   def rwPortToBundle(mem: DefMemory) ={
     val defaultSeq = defaultPortSeq(mem) ++ Seq(
@@ -162,9 +172,24 @@ object MemPortUtils {
       else defaultSeq
     )
   }
+  def rwPortToFlattenBundle(mem: DefMemory) ={
+    val defaultSeq = defaultPortSeq(mem) ++ Seq(
+      Field("wmode", Default, UIntType(IntWidth(1))),
+      Field("wdata", Default, flattenType(mem.dataType)),
+      Field("rdata", Flip, flattenType(mem.dataType))
+    )
+    BundleType(
+      if (containsInfo(mem.info,"maskGran")) defaultSeq :+ Field("wmask", Default, flattenType(create_mask(mem.dataType)))
+      else defaultSeq
+    )
+  }
 
   def memToBundle(s: DefMemory) = BundleType(
     s.readers.map(p => Field(p, Default, rPortToBundle(s))) ++
       s.writers.map(p => Field(p, Default, wPortToBundle(s))) ++
       s.readwriters.map(p => Field(p, Default, rwPortToBundle(s))))
+  def memToFlattenBundle(s: DefMemory) = BundleType(
+    s.readers.map(p => Field(p, Default, rPortToFlattenBundle(s))) ++
+      s.writers.map(p => Field(p, Default, wPortToFlattenBundle(s))) ++
+      s.readwriters.map(p => Field(p, Default, rwPortToFlattenBundle(s))))
 }
diff --git a/src/main/scala/firrtl/passes/ReplaceMemMacros.scala b/src/main/scala/firrtl/passes/ReplaceMemMacros.scala
index c1d54964..fedc4c56 100644
--- a/src/main/scala/firrtl/passes/ReplaceMemMacros.scala
+++ b/src/main/scala/firrtl/passes/ReplaceMemMacros.scala
@@ -6,6 +6,7 @@ import AnalysisUtils._
 import MemTransformUtils._
 import firrtl._
 import firrtl.Utils._
+import MemPortUtils._
 
 object ReplaceMemMacros extends Pass {
 
@@ -65,8 +66,10 @@ object ReplaceMemMacros extends Pass {
     val bbName = m.name + "_ext"
     val stmts = ArrayBuffer[Statement]()
     val wrapperioPorts = MemPortUtils.memToBundle(m).fields.map(f => Port(NoInfo, f.name, Input, f.tpe)) 
-    val bbProto = m.copy(dataType = UIntType(IntWidth(bitWidth(m.dataType))))
-    val bbioPorts = MemPortUtils.memToBundle(bbProto).fields.map(f => Port(NoInfo, f.name, Input, f.tpe)) 
+    val bbProto = m.copy(dataType = flattenType(m.dataType))
+    //val bbioPorts = MemPortUtils.memToBundle(bbProto).fields.map(f => Port(NoInfo, f.name, Input, f.tpe)) 
+    val bbioPorts = MemPortUtils.memToFlattenBundle(m).fields.map(f => Port(NoInfo, f.name, Input, f.tpe)) 
+
     stmts += WDefInstance(m.info,bbName,bbName,UnknownType)
     val bbRef = createRef(bbName)
     stmts ++= (m.readers zip bbProto.readers).map{ 
@@ -80,7 +83,7 @@ object ReplaceMemMacros extends Pass {
     }.flatten  
     val wrapper = Module(m.info,m.name,wrapperioPorts,Block(stmts))   
 
-    println(wrapper.body.serialize)
+    //println(wrapper.body.serialize)
 
     val bb = ExtModule(m.info,bbName,bbioPorts) 
     Seq(bb,wrapper)
@@ -107,12 +110,17 @@ object ReplaceMemMacros extends Pass {
         toBits(WSubField(aggPort,"data",aggMem.dataType,UNKNOWNGENDER))
       )
     )
-    if (containsInfo(aggMem.info,"maskGran"))
+    if (containsInfo(aggMem.info,"maskGran")) {
+      val wrapperMask = create_mask(aggMem.dataType)
+      val bbMask = flattenType(wrapperMask)
       defaultSeq :+ Connect(
         NoInfo,
-        WSubField(groundPort,"mask",create_mask(groundMem.dataType),UNKNOWNGENDER),
-        toBitMask(WSubField(aggPort,"mask",create_mask(aggMem.dataType),UNKNOWNGENDER),aggMem.dataType)
+        //WSubField(groundPort,"mask",create_mask(groundMem.dataType),UNKNOWNGENDER),
+        //toBitMask(WSubField(aggPort,"mask",create_mask(aggMem.dataType),UNKNOWNGENDER),aggMem.dataType)
+        WSubField(groundPort,"mask",bbMask,UNKNOWNGENDER),
+        toBits(WSubField(aggPort,"mask",wrapperMask,UNKNOWNGENDER))
       )
+    }
     else defaultSeq
   }
 
@@ -132,12 +140,17 @@ object ReplaceMemMacros extends Pass {
         WSubField(groundPort,"rdata",groundMem.dataType,UNKNOWNGENDER)
       )
     )
-    if (containsInfo(aggMem.info,"maskGran"))
+    if (containsInfo(aggMem.info,"maskGran")){
+      val wrapperMask = create_mask(aggMem.dataType)
+      val bbMask = flattenType(wrapperMask)
       defaultSeq :+ Connect(
         NoInfo,
-        WSubField(groundPort,"wmask",create_mask(groundMem.dataType),UNKNOWNGENDER),
-        toBitMask(WSubField(aggPort,"wmask",create_mask(aggMem.dataType),UNKNOWNGENDER),aggMem.dataType)
+        //WSubField(groundPort,"wmask",create_mask(groundMem.dataType),UNKNOWNGENDER),
+        //toBitMask(WSubField(aggPort,"wmask",create_mask(aggMem.dataType),UNKNOWNGENDER),aggMem.dataType)
+        WSubField(groundPort,"wmask",bbMask,UNKNOWNGENDER),
+        toBits(WSubField(aggPort,"wmask",wrapperMask,UNKNOWNGENDER))
       )
+    }
     else defaultSeq
   }