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authorJack Koenig2016-02-24 16:57:37 -0800
committerJack Koenig2016-02-24 16:57:37 -0800
commitbcb765aac9732123b4cb3d6eb4c397015b384502 (patch)
treebcd394027994000dcffa05706557f90782e34aa2 /src
parent51502fc37fd74a9990ad68be021bf25b9c829689 (diff)
parented5ce657b79c2b834a70481424f1d86d937daa13 (diff)
Merge pull request #72 from ucb-bar/fix-printf
Quick fix for printf in the emitted Verilog
Diffstat (limited to 'src')
-rw-r--r--src/main/scala/firrtl/Emitter.scala15
1 files changed, 14 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala
index c7bf45a2..04552de4 100644
--- a/src/main/scala/firrtl/Emitter.scala
+++ b/src/main/scala/firrtl/Emitter.scala
@@ -362,8 +362,21 @@ object VerilogEmitter extends Emitter {
Seq("$fdisplay(32'h80000002,\"",ret,"\");$finish;")
}
def printf (str:String,args:Seq[Expression]) : Seq[Any] = {
+ def emitArg(exp: Expression): String = {
+ exp match {
+ case v: UIntValue => s"${v.width match {
+ case w: IntWidth => w.width.toString
+ }}'H${v.value.toString(16)}"
+ case v: SIntValue => s"${v.width match {
+ case w: IntWidth => w.width.toString
+ }}'sH${v.value.toString(16)}"
+ case r: Ref => r.name
+ case r: WRef => r.name
+ case _ => error("Unexpected expression in printf: " + exp.serialize)
+ }
+ }
val q = '"'.toString
- val strx = (Seq(q + escape(str) + q) ++ args.map(x => escape(x.serialize()))).reduce(_ + "," + _)
+ val strx = (Seq(q + escape(str) + q) ++ args.map(x => emitArg(x))).reduce(_ + "," + _)
Seq("$fwrite(32'h80000002,",strx,");")
}
def delay (e:Expression, n:Int, clk:Expression) : Expression = {