remove Utils.tpe

9 files changed, 126 insertions, 144 deletions

diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala
index a4f5c14d..e6314b72 100644
--- a/src/main/scala/firrtl/Emitter.scala
+++ b/src/main/scala/firrtl/Emitter.scala
@@ -70,7 +70,7 @@ class VerilogEmitter extends Emitter {
    def remove_root (ex:Expression) : Expression = {
       (ex.as[WSubField].get.exp) match {
          case (e:WSubField) => remove_root(e)
-         case (e:WRef) => WRef(ex.as[WSubField].get.name,tpe(ex),InstanceKind(),UNKNOWNGENDER)
+         case (e:WRef) => WRef(ex.as[WSubField].get.name,ex.tpe,InstanceKind(),UNKNOWNGENDER)
       }
    }
    def not_empty (s:ArrayBuffer[_]) : Boolean = if (s.size == 0) false else true
@@ -142,9 +142,9 @@ class VerilogEmitter extends Emitter {
    }
    def op_stream (doprim:DoPrim) : Seq[Any] = {
       def cast_if (e:Expression) : Any = {
-         val signed = doprim.args.find(x => tpe(x).typeof[SIntType])
+         val signed = doprim.args.find(x => x.tpe.typeof[SIntType])
          if (signed == None) e
-         else tpe(e) match {
+         else e.tpe match {
             case (t:SIntType) => Seq("$signed(",e,")")
             case (t:UIntType) => Seq("$signed({1'b0,",e,"})")
          }
@@ -156,7 +156,7 @@ class VerilogEmitter extends Emitter {
          }
       }
       def cast_as (e:Expression) : Any = {
-         (tpe(e)) match {
+         (e.tpe) match {
             case (t:UIntType) => e
             case (t:SIntType) => Seq("$signed(",e,")")
          }
@@ -192,7 +192,7 @@ class VerilogEmitter extends Emitter {
          case Eq => Seq(cast_if(a0())," == ", cast_if(a1()))
          case Neq => Seq(cast_if(a0())," != ", cast_if(a1()))
          case Pad => {
-            val w = long_BANG(tpe(a0()))
+            val w = long_BANG(a0().tpe)
             val diff = (c0() - w)
             if (w == 0) Seq(a0())
             else doprim.tpe match {
@@ -219,13 +219,13 @@ class VerilogEmitter extends Emitter {
          case Shlw => Seq(cast(a0())," << ", c0())
          case Shl => Seq(cast(a0())," << ",c0())
          case Shr => {
-           if (c0 >= long_BANG(tpe(a0)))
+           if (c0 >= long_BANG(a0.tpe))
              error("Verilog emitter does not support SHIFT_RIGHT >= arg width")
-           Seq(a0(),"[", long_BANG(tpe(a0())) - 1,":",c0(),"]")
+           Seq(a0(),"[", long_BANG(a0().tpe) - 1,":",c0(),"]")
          }
          case Neg => Seq("-{",cast(a0()),"}")
          case Cvt => {
-            tpe(a0()) match {
+            a0().tpe match {
                case (t:UIntType) => Seq("{1'b0,",cast(a0()),"}")
                case (t:SIntType) => Seq(cast(a0()))
             }
@@ -258,18 +258,18 @@ class VerilogEmitter extends Emitter {
          case Cat => Seq("{",cast(a0()),",",cast(a1()),"}")
          case Bits => {
             // If selecting zeroth bit and single-bit wire, just emit the wire
-            if (c0() == 0 && c1() == 0 && long_BANG(tpe(a0())) == 1) Seq(a0())
+            if (c0() == 0 && c1() == 0 && long_BANG(a0().tpe) == 1) Seq(a0())
             else if (c0() == c1()) Seq(a0(),"[",c0(),"]")
             else Seq(a0(),"[",c0(),":",c1(),"]")
          }
          case Head => {
-            val w = long_BANG(tpe(a0()))
+            val w = long_BANG(a0().tpe)
             val high = w - 1
             val low = w - c0()
             Seq(a0(),"[",high,":",low,"]")
          }
          case Tail => {
-            val w = long_BANG(tpe(a0()))
+            val w = long_BANG(a0().tpe)
             val low = w - c0() - 1
             Seq(a0(),"[",low,":",0,"]")
          }
@@ -286,7 +286,7 @@ class VerilogEmitter extends Emitter {
             case (s:Connect) => netlist(s.loc) = s.expr
             case (s:IsInvalid) => {
                val n = namespace.newTemp
-               val e = wref(n,tpe(s.expr))
+               val e = wref(n,s.expr.tpe)
                netlist(s.expr) = e
             }
             case (s:Conditionally) => simlist += s
@@ -319,12 +319,12 @@ class VerilogEmitter extends Emitter {
          assigns += Seq("`ifndef RANDOMIZE_GARBAGE_ASSIGN")
          assigns += Seq("assign ", e, " = ", syn, ";")
          assigns += Seq("`else")
-         assigns += Seq("assign ", e, " = ", garbageCond, " ? ", rand_string(tpe(syn)), " : ", syn, ";")
+         assigns += Seq("assign ", e, " = ", garbageCond, " ? ", rand_string(syn.tpe), " : ", syn, ";")
          assigns += Seq("`endif")
       }
       def invalidAssign(e: Expression) = {
         assigns += Seq("`ifdef RANDOMIZE_INVALID_ASSIGN")
-        assigns += Seq("assign ", e, " = ", rand_string(tpe(e)), ";")
+        assigns += Seq("assign ", e, " = ", rand_string(e.tpe), ";")
         assigns += Seq("`endif")
       }
       def update_and_reset(r: Expression, clk: Expression, reset: Expression, init: Expression) = {
@@ -387,7 +387,7 @@ class VerilogEmitter extends Emitter {
       }
       def initialize(e: Expression) = {
         initials += Seq("`ifdef RANDOMIZE_REG_INIT")
-        initials += Seq(e, " = ", rand_string(tpe(e)), ";")
+        initials += Seq(e, " = ", rand_string(e.tpe), ";")
         initials += Seq("`endif")
       }
       def initialize_mem(s: DefMemory) = {
@@ -407,8 +407,8 @@ class VerilogEmitter extends Emitter {
          }}
          instdeclares += Seq(");")
          for (e <- es) {
-            declare("wire",LowerTypes.loweredName(e),tpe(e))
-            val ex = WRef(LowerTypes.loweredName(e),tpe(e),kind(e),gender(e))
+            declare("wire",LowerTypes.loweredName(e),e.tpe)
+            val ex = WRef(LowerTypes.loweredName(e),e.tpe,kind(e),gender(e))
             if (gender(e) == FEMALE) {
                assign(ex,netlist(e))
             }
@@ -444,8 +444,8 @@ class VerilogEmitter extends Emitter {
       def delay (e:Expression, n:Int, clk:Expression) : Expression = {
          ((0 until n) foldLeft e){(ex, i) =>
             val name = namespace.newTemp
-            declare("reg",name,tpe(e))
-            val exx = WRef(name,tpe(e),ExpKind(),UNKNOWNGENDER)
+            declare("reg",name,e.tpe)
+            val exx = WRef(name,e.tpe,ExpKind(),UNKNOWNGENDER)
             initialize(exx)
             update(exx,ex,clk,one)
             exx
@@ -479,12 +479,12 @@ class VerilogEmitter extends Emitter {
             }
             case (s:IsInvalid) => {
                val wref = netlist(s.expr).as[WRef].get
-               declare("wire",wref.name,tpe(s.expr))
+               declare("wire",wref.name,s.expr.tpe)
                invalidAssign(wref)
             }
             case (s:DefNode) => {
-               declare("wire",s.name,tpe(s.value))
-               assign(WRef(s.name,tpe(s.value),NodeKind(),MALE),s.value)
+               declare("wire",s.name,s.value.tpe)
+               assign(WRef(s.name,s.value.tpe,NodeKind(),MALE),s.value)
             }
             case (s:Stop) => {
               val errorString = StringLit(s"${s.ret}\n".getBytes)
@@ -513,9 +513,9 @@ class VerilogEmitter extends Emitter {
                   //Ports should share an always@posedge, so can't have intermediary wire
                   val clk = netlist(mem_exp(r,"clk")) 
                   
-                  declare("wire",LowerTypes.loweredName(data),tpe(data))
-                  declare("wire",LowerTypes.loweredName(addr),tpe(addr))
-                  declare("wire",LowerTypes.loweredName(en),tpe(en))
+                  declare("wire",LowerTypes.loweredName(data),data.tpe)
+                  declare("wire",LowerTypes.loweredName(addr),addr.tpe)
+                  declare("wire",LowerTypes.loweredName(en),en.tpe)
 
                   //; Read port
                   assign(addr,netlist(addr)) //;Connects value to m.r.addr
@@ -524,8 +524,8 @@ class VerilogEmitter extends Emitter {
                   val en_pipe = if (weq(en,one)) one else delay(en,s.readLatency-1,clk)
                   val addrx = if (s.readLatency > 0) {
                     val name = namespace.newTemp
-                    val ref = WRef(name,tpe(addr),ExpKind(),UNKNOWNGENDER)
-                    declare("reg",name,tpe(addr))
+                    val ref = WRef(name,addr.tpe,ExpKind(),UNKNOWNGENDER)
+                    declare("reg",name,addr.tpe)
                     initialize(ref)
                     update(ref,addr_pipe,clk,en_pipe)
                     ref
@@ -548,10 +548,10 @@ class VerilogEmitter extends Emitter {
                   //Ports should share an always@posedge, so can't have intermediary wire
                   val clk = netlist(mem_exp(w,"clk"))
                   
-                  declare("wire",LowerTypes.loweredName(data),tpe(data))
-                  declare("wire",LowerTypes.loweredName(addr),tpe(addr))
-                  declare("wire",LowerTypes.loweredName(mask),tpe(mask))
-                  declare("wire",LowerTypes.loweredName(en),tpe(en))
+                  declare("wire",LowerTypes.loweredName(data),data.tpe)
+                  declare("wire",LowerTypes.loweredName(addr),addr.tpe)
+                  declare("wire",LowerTypes.loweredName(mask),mask.tpe)
+                  declare("wire",LowerTypes.loweredName(en),en.tpe)
    
                   //; Write port
                   assign(data,netlist(data))
@@ -577,12 +577,12 @@ class VerilogEmitter extends Emitter {
                   //Ports should share an always@posedge, so can't have intermediary wire
                   val clk = netlist(mem_exp(rw,"clk"))
                   
-                  declare("wire",LowerTypes.loweredName(wmode),tpe(wmode))
-                  declare("wire",LowerTypes.loweredName(rdata),tpe(rdata))
-                  declare("wire",LowerTypes.loweredName(wdata),tpe(wdata))
-                  declare("wire",LowerTypes.loweredName(wmask),tpe(wmask))
-                  declare("wire",LowerTypes.loweredName(addr),tpe(addr))
-                  declare("wire",LowerTypes.loweredName(en),tpe(en))
+                  declare("wire",LowerTypes.loweredName(wmode),wmode.tpe)
+                  declare("wire",LowerTypes.loweredName(rdata),rdata.tpe)
+                  declare("wire",LowerTypes.loweredName(wdata),wdata.tpe)
+                  declare("wire",LowerTypes.loweredName(wmask),wmask.tpe)
+                  declare("wire",LowerTypes.loweredName(addr),addr.tpe)
+                  declare("wire",LowerTypes.loweredName(en),en.tpe)
    
                   //; Assigned to lowered wires of each
                   assign(addr,netlist(addr))
@@ -602,8 +602,8 @@ class VerilogEmitter extends Emitter {
 
                   val raddrxx = if (s.readLatency > 0) {
                     val name = namespace.newTemp
-                    val ref = WRef(name,tpe(raddrx),ExpKind(),UNKNOWNGENDER)
-                    declare("reg",name,tpe(raddrx))
+                    val ref = WRef(name,raddrx.tpe,ExpKind(),UNKNOWNGENDER)
+                    declare("reg",name,raddrx.tpe)
                     initialize(ref)
                     ref
                   } else addr
@@ -613,8 +613,8 @@ class VerilogEmitter extends Emitter {
 
                   def declare_and_assign(exp: Expression) = {
                     val name = namespace.newTemp
-                    val ref = wref(name, tpe(exp))
-                    declare("wire", name, tpe(exp))
+                    val ref = wref(name, exp.tpe)
+                    declare("wire", name, exp.tpe)
                     assign(ref, exp)
                     ref
                   }
diff --git a/src/main/scala/firrtl/Utils.scala b/src/main/scala/firrtl/Utils.scala
index 9d27641d..ca2577b6 100644
--- a/src/main/scala/firrtl/Utils.scala
+++ b/src/main/scala/firrtl/Utils.scala
@@ -126,7 +126,7 @@ object Utils extends LazyLogging {
       else if (e2 == we(zero)) e1.e1
       else DoPrim(Or,Seq(e1.e1,e2.e1),Seq(),UIntType(IntWidth(1)))
    }
-   def EQV (e1:Expression,e2:Expression) : Expression = { DoPrim(Eq,Seq(e1,e2),Seq(),tpe(e1)) }
+   def EQV (e1:Expression,e2:Expression) : Expression = { DoPrim(Eq,Seq(e1,e2),Seq(),e1.tpe) }
    def NOT (e1:WrappedExpression) : Expression = {
       if (e1 == we(one)) zero
       else if (e1 == we(zero)) one
@@ -135,7 +135,7 @@ object Utils extends LazyLogging {
 
    
    //def MUX (p:Expression,e1:Expression,e2:Expression) : Expression = {
-   //   Mux(p,e1,e2,mux_type(tpe(e1),tpe(e2)))
+   //   Mux(p,e1,e2,mux_type(e1.tpe,e2.tpe))
    //}
 
    def create_mask (dt:Type) : Type = {
@@ -156,8 +156,8 @@ object Utils extends LazyLogging {
          val e1s = create_exps(e.tval)
          val e2s = create_exps(e.fval)
          (e1s,e2s).zipped map ((e1,e2) => Mux(e.cond,e1,e2,mux_type_and_widths(e1,e2)))
-      case (e:ValidIf) => create_exps(e.value) map (e1 => ValidIf(e.cond,e1,tpe(e1)))
-      case (e) => tpe(e) match {
+      case (e:ValidIf) => create_exps(e.value) map (e1 => ValidIf(e.cond,e1,e1.tpe))
+      case (e) => e.tpe match {
          case (_:GroundType) => Seq(e)
          case (t:BundleType) => (t.fields foldLeft Seq[Expression]())((exps, f) =>
             exps ++ create_exps(WSubField(e,f.name,f.tpe,times(gender(e), f.flip))))
@@ -193,7 +193,7 @@ object Utils extends LazyLogging {
   
    def get_point (e:Expression) : Int = e match {
      case (e: WRef) => 0
-     case (e: WSubField) => tpe(e.exp) match {case b: BundleType =>
+     case (e: WSubField) => e.exp.tpe match {case b: BundleType =>
        (b.fields takeWhile (_.name != e.name) foldLeft 0)(
          (point, f) => point + get_size(f.tpe))
      }
@@ -214,7 +214,7 @@ object Utils extends LazyLogging {
    }
 
 //============== TYPES ================
-   def mux_type (e1:Expression,e2:Expression) : Type = mux_type(tpe(e1),tpe(e2))
+   def mux_type (e1:Expression,e2:Expression) : Type = mux_type(e1.tpe,e2.tpe)
    def mux_type (t1:Type,t2:Type) : Type = {
       if (wt(t1) == wt(t2)) {
          (t1,t2) match { 
@@ -228,7 +228,7 @@ object Utils extends LazyLogging {
          }
       } else UnknownType
    }
-   def mux_type_and_widths (e1:Expression,e2:Expression) : Type = mux_type_and_widths(tpe(e1),tpe(e2))
+   def mux_type_and_widths (e1:Expression,e2:Expression) : Type = mux_type_and_widths(e1.tpe,e2.tpe)
    def mux_type_and_widths (t1:Type,t2:Type) : Type = {
       def wmax (w1:Width,w2:Width) : Width = {
          (w1,w2) match {
@@ -497,29 +497,11 @@ object Utils extends LazyLogging {
          case e:WSubIndex => kind(e.exp)
          case e => ExpKind()
       }
-   def tpe (e:Expression) : Type =
-      e match {
-         case e:Reference => e.tpe
-         case e:SubField => e.tpe
-         case e:SubIndex => e.tpe
-         case e:SubAccess => e.tpe
-         case e:WRef => e.tpe
-         case e:WSubField => e.tpe
-         case e:WSubIndex => e.tpe
-         case e:WSubAccess => e.tpe
-         case e:DoPrim => e.tpe
-         case e:Mux => e.tpe
-         case e:ValidIf => e.tpe
-         case e:UIntLiteral => UIntType(e.width)
-         case e:SIntLiteral => SIntType(e.width)
-         case e:WVoid => UnknownType
-         case e:WInvalid => UnknownType
-      }
    def get_type (s:Statement) : Type = {
       s match {
        case s:DefWire => s.tpe
        case s:DefRegister => s.tpe
-       case s:DefNode => tpe(s.value)
+       case s:DefNode => s.value.tpe
        case s:DefMemory => {
           val depth = s.depth
           val addr = Field("addr",Default,UIntType(IntWidth(scala.math.max(ceil_log2(depth), 1))))
diff --git a/src/main/scala/firrtl/passes/Checks.scala b/src/main/scala/firrtl/passes/Checks.scala
index 9ee20c0a..e61c55ea 100644
--- a/src/main/scala/firrtl/passes/Checks.scala
+++ b/src/main/scala/firrtl/passes/Checks.scala
@@ -336,27 +336,27 @@ object CheckTypes extends Pass with LazyLogging {
       def all_same_type (ls:Seq[Expression]) : Unit = {
          var error = false
          for (x <- ls) {
-            if (wt(tpe(ls.head)) != wt(tpe(x))) error = true
+            if (wt(ls.head.tpe) != wt(x.tpe)) error = true
          }
          if (error) errors.append(new OpNotAllSameType(info,e.op.serialize))
       }
       def all_ground (ls:Seq[Expression]) : Unit = {
          var error = false
          for (x <- ls ) {
-            if (!(tpe(x).typeof[UIntType] || tpe(x).typeof[SIntType])) error = true
+            if (!(x.tpe.typeof[UIntType] || x.tpe.typeof[SIntType])) error = true
          }
          if (error) errors.append(new OpNotGround(info,e.op.serialize))
       }
       def all_uint (ls:Seq[Expression]) : Unit = {
          var error = false
          for (x <- ls ) {
-            if (!(tpe(x).typeof[UIntType])) error = true
+            if (!(x.tpe.typeof[UIntType])) error = true
          }
          if (error) errors.append(new OpNotAllUInt(info,e.op.serialize))
       }
       def is_uint (x:Expression) : Unit = {
          var error = false
-         if (!(tpe(x).typeof[UIntType])) error = true
+         if (!(x.tpe.typeof[UIntType])) error = true
          if (error) errors.append(new OpNotUInt(info,e.op.serialize,x.serialize))
       }
       
@@ -417,7 +417,7 @@ object CheckTypes extends Pass with LazyLogging {
          (e map (check_types_e(info))) match { 
             case (e:WRef) => e
             case (e:WSubField) => {
-               (tpe(e.exp)) match  { 
+               (e.exp.tpe) match  { 
                   case (t:BundleType) => {
                      val ft = t.fields.find(p => p.name == e.name)
                      if (ft == None) errors.append(new SubfieldNotInBundle(info,e.name))
@@ -426,7 +426,7 @@ object CheckTypes extends Pass with LazyLogging {
                }
             }
             case (e:WSubIndex) => {
-               (tpe(e.exp)) match { 
+               (e.exp.tpe) match { 
                   case (t:VectorType) => {
                      if (e.value >= t.size) errors.append(new IndexTooLarge(info,e.value))
                   }
@@ -434,24 +434,24 @@ object CheckTypes extends Pass with LazyLogging {
                }
             }
             case (e:WSubAccess) => {
-               (tpe(e.exp)) match { 
+               (e.exp.tpe) match { 
                   case (t:VectorType) => false
                   case (t) => errors.append(new IndexOnNonVector(info))
                }
-               (tpe(e.index)) match { 
+               (e.index.tpe) match { 
                   case (t:UIntType) => false
                   case (t) => errors.append(new AccessIndexNotUInt(info))
                }
             }
             case (e:DoPrim) => check_types_primop(e,errors,info)
             case (e:Mux) => {
-               if (wt(tpe(e.tval)) != wt(tpe(e.fval))) errors.append(new MuxSameType(info))
-               if (!passive(tpe(e))) errors.append(new MuxPassiveTypes(info))
-               if (!(tpe(e.cond).typeof[UIntType])) errors.append(new MuxCondUInt(info))
+               if (wt(e.tval.tpe) != wt(e.fval.tpe)) errors.append(new MuxSameType(info))
+               if (!passive(e.tpe)) errors.append(new MuxPassiveTypes(info))
+               if (!(e.cond.tpe.typeof[UIntType])) errors.append(new MuxCondUInt(info))
             }
             case (e:ValidIf) => {
-               if (!passive(tpe(e))) errors.append(new ValidIfPassiveTypes(info))
-               if (!(tpe(e.cond).typeof[UIntType])) errors.append(new ValidIfCondUInt(info))
+               if (!passive(e.tpe)) errors.append(new ValidIfPassiveTypes(info))
+               if (!(e.cond.tpe.typeof[UIntType])) errors.append(new ValidIfCondUInt(info))
             }
             case (_:UIntLiteral | _:SIntLiteral) => false
          }
@@ -484,22 +484,22 @@ object CheckTypes extends Pass with LazyLogging {
 
       def check_types_s (s:Statement) : Statement = {
          s map (check_types_e(get_info(s))) match { 
-            case (s:Connect) => if (wt(tpe(s.loc)) != wt(tpe(s.expr))) errors.append(new InvalidConnect(s.info, s.loc.serialize, s.expr.serialize))
-            case (s:DefRegister) => if (wt(s.tpe) != wt(tpe(s.init))) errors.append(new InvalidRegInit(s.info))
-            case (s:PartialConnect) => if (!bulk_equals(tpe(s.loc),tpe(s.expr),Default,Default) ) errors.append(new InvalidConnect(s.info, s.loc.serialize, s.expr.serialize))
+            case (s:Connect) => if (wt(s.loc.tpe) != wt(s.expr.tpe)) errors.append(new InvalidConnect(s.info, s.loc.serialize, s.expr.serialize))
+            case (s:DefRegister) => if (wt(s.tpe) != wt(s.init.tpe)) errors.append(new InvalidRegInit(s.info))
+            case (s:PartialConnect) => if (!bulk_equals(s.loc.tpe,s.expr.tpe,Default,Default) ) errors.append(new InvalidConnect(s.info, s.loc.serialize, s.expr.serialize))
             case (s:Stop) => {
-               if (wt(tpe(s.clk)) != wt(ClockType) ) errors.append(new ReqClk(s.info))
-               if (wt(tpe(s.en)) != wt(ut()) ) errors.append(new EnNotUInt(s.info))
+               if (wt(s.clk.tpe) != wt(ClockType) ) errors.append(new ReqClk(s.info))
+               if (wt(s.en.tpe) != wt(ut()) ) errors.append(new EnNotUInt(s.info))
             }
             case (s:Print)=> {
                for (x <- s.args ) {
-                  if (wt(tpe(x)) != wt(ut()) && wt(tpe(x)) != wt(st()) ) errors.append(new PrintfArgNotGround(s.info))
+                  if (wt(x.tpe) != wt(ut()) && wt(x.tpe) != wt(st()) ) errors.append(new PrintfArgNotGround(s.info))
                }
-               if (wt(tpe(s.clk)) != wt(ClockType) ) errors.append(new ReqClk(s.info))
-               if (wt(tpe(s.en)) != wt(ut()) ) errors.append(new EnNotUInt(s.info))
+               if (wt(s.clk.tpe) != wt(ClockType) ) errors.append(new ReqClk(s.info))
+               if (wt(s.en.tpe) != wt(ut()) ) errors.append(new EnNotUInt(s.info))
             }
-            case (s:Conditionally) => if (wt(tpe(s.pred)) != wt(ut()) ) errors.append(new PredNotUInt(s.info))
-            case (s:DefNode) => if (!passive(tpe(s.value)) ) errors.append(new NodePassiveType(s.info))
+            case (s:Conditionally) => if (wt(s.pred.tpe) != wt(ut()) ) errors.append(new PredNotUInt(s.info))
+            case (s:DefNode) => if (!passive(s.value.tpe) ) errors.append(new NodePassiveType(s.info))
             case (s) => false
          }
          s map (check_types_s)
@@ -571,7 +571,7 @@ object CheckGenders extends Pass {
             fQ
          }
             
-         val has_flipQ = flipQ(tpe(e))
+         val has_flipQ = flipQ(e.tpe)
          //println(e)
          //println(gender)
          //println(desired)
@@ -597,7 +597,7 @@ object CheckGenders extends Pass {
          (e) match { 
             case (e:WRef) => genders(e.name)
             case (e:WSubField) => 
-               val f = tpe(e.exp).as[BundleType].get.fields.find(f => f.name == e.name).get
+               val f = e.exp.tpe.as[BundleType].get.fields.find(f => f.name == e.name).get
                times(get_gender(e.exp,genders),f.flip)
             case (e:WSubIndex) => get_gender(e.exp,genders)
             case (e:WSubAccess) => get_gender(e.exp,genders)
diff --git a/src/main/scala/firrtl/passes/ConstProp.scala b/src/main/scala/firrtl/passes/ConstProp.scala
index 57782a3c..2e8b53f3 100644
--- a/src/main/scala/firrtl/passes/ConstProp.scala
+++ b/src/main/scala/firrtl/passes/ConstProp.scala
@@ -129,7 +129,7 @@ object ConstProp extends Pass {
 
   private def foldComparison(e: DoPrim) = {
     def foldIfZeroedArg(x: Expression): Expression = {
-      def isUInt(e: Expression): Boolean = tpe(e) match {
+      def isUInt(e: Expression): Boolean = e.tpe match {
         case UIntType(_) => true
         case _ => false
       }
@@ -163,7 +163,7 @@ object ConstProp extends Pass {
       def range(e: Expression): Range = e match {
         case UIntLiteral(value, _) => Range(value, value)
         case SIntLiteral(value, _) => Range(value, value)
-        case _ => tpe(e) match {
+        case _ => e.tpe match {
           case SIntType(IntWidth(width)) => Range(
             min = BigInt(0) - BigInt(2).pow(width.toInt - 1),
             max = BigInt(2).pow(width.toInt - 1) - BigInt(1)
@@ -226,7 +226,7 @@ object ConstProp extends Pass {
     case Pad => e.args(0) match {
       case UIntLiteral(v, _) => UIntLiteral(v, IntWidth(e.consts(0)))
       case SIntLiteral(v, _) => SIntLiteral(v, IntWidth(e.consts(0)))
-      case _ if long_BANG(tpe(e.args(0))) == e.consts(0) => e.args(0)
+      case _ if long_BANG(e.args(0).tpe) == e.consts(0) => e.args(0)
       case _ => e
     }
     case Bits => e.args(0) match {
@@ -234,9 +234,9 @@ object ConstProp extends Pass {
         val hi = e.consts(0).toInt
         val lo = e.consts(1).toInt
         require(hi >= lo)
-        UIntLiteral((lit.value >> lo) & ((BigInt(1) << (hi - lo + 1)) - 1), widthBANG(tpe(e)))
+        UIntLiteral((lit.value >> lo) & ((BigInt(1) << (hi - lo + 1)) - 1), widthBANG(e.tpe))
       }
-      case x if long_BANG(tpe(e)) == long_BANG(tpe(x)) => tpe(x) match {
+      case x if long_BANG(e.tpe) == long_BANG(x.tpe) => x.tpe match {
         case t: UIntType => x
         case _ => asUInt(x, e.tpe)
       }
diff --git a/src/main/scala/firrtl/passes/ExpandWhens.scala b/src/main/scala/firrtl/passes/ExpandWhens.scala
index 921693c7..3d26298a 100644
--- a/src/main/scala/firrtl/passes/ExpandWhens.scala
+++ b/src/main/scala/firrtl/passes/ExpandWhens.scala
@@ -131,8 +131,8 @@ object ExpandWhens extends Pass {
                   val falseValue = altNetlist.getOrElse(lvalue, defaultValue)
                   (trueValue, falseValue) match {
                     case (WInvalid(), WInvalid()) => WInvalid()
-                    case (WInvalid(), fv) => ValidIf(NOT(s.pred), fv, tpe(fv))
-                    case (tv, WInvalid()) => ValidIf(s.pred, tv, tpe(tv))
+                    case (WInvalid(), fv) => ValidIf(NOT(s.pred), fv, fv.tpe)
+                    case (tv, WInvalid()) => ValidIf(s.pred, tv, tv.tpe)
                     case (tv, fv) => Mux(s.pred, tv, fv, mux_type_and_widths(tv, fv))
                   }
                 case None =>
diff --git a/src/main/scala/firrtl/passes/LowerTypes.scala b/src/main/scala/firrtl/passes/LowerTypes.scala
index 585598a8..e5661fae 100644
--- a/src/main/scala/firrtl/passes/LowerTypes.scala
+++ b/src/main/scala/firrtl/passes/LowerTypes.scala
@@ -138,7 +138,7 @@ object LowerTypes extends Pass {
           case k: InstanceKind =>
             val (root, tail) = splitRef(e)
             val name = loweredName(tail)
-            WSubField(root, name, tpe(e), gender(e))
+            WSubField(root, name, e.tpe, gender(e))
           case k: MemKind =>
             val exps = lowerTypesMemExp(e)
             if (exps.length > 1)
@@ -146,7 +146,7 @@ object LowerTypes extends Pass {
                     " to be expanded!")
             exps(0)
           case k =>
-            WRef(loweredName(e), tpe(e), kind(e), gender(e))
+            WRef(loweredName(e), e.tpe, kind(e), gender(e))
         }
         case e: Mux => e map (lowerTypesExp)
         case e: ValidIf => e map (lowerTypesExp)
@@ -162,7 +162,7 @@ object LowerTypes extends Pass {
               s
             } else {
               val exps = create_exps(s.name, s.tpe)
-              val stmts = exps map (e => DefWire(s.info, loweredName(e), tpe(e)))
+              val stmts = exps map (e => DefWire(s.info, loweredName(e), e.tpe))
               Block(stmts)
             }
           case s: DefRegister =>
@@ -175,7 +175,7 @@ object LowerTypes extends Pass {
               val clock = lowerTypesExp(s.clock)
               val reset = lowerTypesExp(s.reset)
               val stmts = es zip inits map { case (e, i) =>
-                DefRegister(s.info, loweredName(e), tpe(e), clock, reset, i)
+                DefRegister(s.info, loweredName(e), e.tpe, clock, reset, i)
               }
               Block(stmts)
             }
@@ -188,7 +188,7 @@ object LowerTypes extends Pass {
                   val exps = create_exps(WRef(f.name, f.tpe, ExpKind(), times(f.flip, MALE)))
                   exps map ( e =>
                     // Flip because inst genders are reversed from Module type
-                    Field(loweredName(e), toFlip(gender(e)).flip, tpe(e))
+                    Field(loweredName(e), toFlip(gender(e)).flip, e.tpe)
                   )
                 }
                 WDefInstance(s.info, s.name, s.module, BundleType(fieldsx))
@@ -202,7 +202,7 @@ object LowerTypes extends Pass {
             } else {
               val exps = create_exps(s.name, s.dataType)
               val stmts = exps map { e =>
-                DefMemory(s.info, loweredName(e), tpe(e), s.depth,
+                DefMemory(s.info, loweredName(e), e.tpe, s.depth,
                   s.writeLatency, s.readLatency, s.readers, s.writers,
                   s.readwriters)
               }
@@ -217,7 +217,7 @@ object LowerTypes extends Pass {
           // node y = x_a
           case s: DefNode =>
             sinfo = s.info
-            val names = create_exps(s.name, tpe(s.value)) map (lowerTypesExp)
+            val names = create_exps(s.name, s.value.tpe) map (lowerTypesExp)
             val exps = create_exps(s.value) map (lowerTypesExp)
             val stmts = names zip exps map { case (n, e) =>
               DefNode(s.info, loweredName(n), e)
@@ -249,7 +249,7 @@ object LowerTypes extends Pass {
       // Lower Ports
       val portsx = m.ports flatMap { p =>
         val exps = create_exps(WRef(p.name, p.tpe, PortKind(), to_gender(p.direction)))
-        exps map ( e => Port(p.info, loweredName(e), to_dir(gender(e)), tpe(e)) )
+        exps map ( e => Port(p.info, loweredName(e), to_dir(gender(e)), e.tpe) )
       }
       m match {
         case m: ExtModule => m.copy(ports = portsx)
diff --git a/src/main/scala/firrtl/passes/PadWidths.scala b/src/main/scala/firrtl/passes/PadWidths.scala
index 0cabc293..f2117761 100644
--- a/src/main/scala/firrtl/passes/PadWidths.scala
+++ b/src/main/scala/firrtl/passes/PadWidths.scala
@@ -2,7 +2,7 @@ package firrtl
 package passes
 
 import firrtl.Mappers.{ExpMap, StmtMap}
-import firrtl.Utils.{tpe, long_BANG}
+import firrtl.Utils.long_BANG
 import firrtl.PrimOps._
 import firrtl.ir._
 
@@ -10,10 +10,10 @@ import firrtl.ir._
 object PadWidths extends Pass {
    def name = "Pad Widths"
    private def width(t: Type): Int = long_BANG(t).toInt
-   private def width(e: Expression): Int = width(tpe(e))
+   private def width(e: Expression): Int = width(e.tpe)
    // Returns an expression with the correct integer width
    private def fixup(i: Int)(e: Expression) = {
-      def tx = tpe(e) match {
+      def tx = e.tpe match {
          case t: UIntType => UIntType(IntWidth(i))
          case t: SIntType => SIntType(IntWidth(i))
          // default case should never be reached
diff --git a/src/main/scala/firrtl/passes/Passes.scala b/src/main/scala/firrtl/passes/Passes.scala
index 7b4f9aa2..ae3d722a 100644
--- a/src/main/scala/firrtl/passes/Passes.scala
+++ b/src/main/scala/firrtl/passes/Passes.scala
@@ -103,7 +103,7 @@ object ResolveKinds extends Pass {
          def resolve (body:Statement) = {
             def resolve_expr (e:Expression):Expression = {
                e match {
-                  case e:WRef => WRef(e.name,tpe(e),kinds(e.name),e.gender)
+                  case e:WRef => WRef(e.name,e.tpe,kinds(e.name),e.gender)
                   case e => e map (resolve_expr)
                }
             }
@@ -170,11 +170,11 @@ object InferTypes extends Pass {
          val types = LinkedHashMap[String,Type]()
          def infer_types_e (e:Expression) : Expression = {
             e map (infer_types_e) match {
-               case e:ValidIf => ValidIf(e.cond,e.value,tpe(e.value))
+               case e:ValidIf => ValidIf(e.cond,e.value,e.value.tpe)
                case e:WRef => WRef(e.name, types(e.name),e.kind,e.gender)
-               case e:WSubField => WSubField(e.exp,e.name,field_type(tpe(e.exp),e.name),e.gender)
-               case e:WSubIndex => WSubIndex(e.exp,e.value,sub_type(tpe(e.exp)),e.gender)
-               case e:WSubAccess => WSubAccess(e.exp,e.index,sub_type(tpe(e.exp)),e.gender)
+               case e:WSubField => WSubField(e.exp,e.name,field_type(e.exp.tpe,e.name),e.gender)
+               case e:WSubIndex => WSubIndex(e.exp,e.value,sub_type(e.exp.tpe),e.gender)
+               case e:WSubAccess => WSubAccess(e.exp,e.index,sub_type(e.exp.tpe),e.gender)
                case e:DoPrim => set_primop_type(e)
                case e:Mux => Mux(e.cond,e.tval,e.fval,mux_type_and_widths(e.tval,e.fval))
                case e:UIntLiteral => e
@@ -246,7 +246,7 @@ object ResolveGenders extends Pass {
             case e:WRef => WRef(e.name,e.tpe,e.kind,g)
             case e:WSubField => {
                val expx = 
-                  field_flip(tpe(e.exp),e.name) match {
+                  field_flip(e.exp.tpe,e.name) match {
                      case Default => resolve_e(g)(e.exp)
                      case Flip => resolve_e(swap(g))(e.exp)
                   }
@@ -474,7 +474,7 @@ object InferWidths extends Pass {
          case (t:SIntType) => t.width
          case ClockType => IntWidth(1)
          case (t) => error("No width!"); IntWidth(-1) } }
-   def width_BANG (e:Expression) : Width = width_BANG(tpe(e))
+   def width_BANG (e:Expression) : Width = width_BANG(e.tpe)
 
    def reduce_var_widths(c: Circuit, h: LinkedHashMap[String,Width]): Circuit = {
       def evaluate(w: Width): Width = {
@@ -556,29 +556,29 @@ object InferWidths extends Pass {
       def get_constraints (s:Statement) : Statement = {
          (s map (get_constraints_e)) match {
             case (s:Connect) => {
-               val n = get_size(tpe(s.loc))
+               val n = get_size(s.loc.tpe)
                val ce_loc = create_exps(s.loc)
                val ce_exp = create_exps(s.expr)
                for (i <- 0 until n) {
                   val locx = ce_loc(i)
                   val expx = ce_exp(i)
-                  get_flip(tpe(s.loc),i,Default) match {
+                  get_flip(s.loc.tpe,i,Default) match {
                      case Default => constrain(width_BANG(locx),width_BANG(expx))
                      case Flip => constrain(width_BANG(expx),width_BANG(locx)) }}
                s }
             case (s:PartialConnect) => {
-               val ls = get_valid_points(tpe(s.loc),tpe(s.expr),Default,Default)
+               val ls = get_valid_points(s.loc.tpe,s.expr.tpe,Default,Default)
                for (x <- ls) {
                   val locx = create_exps(s.loc)(x._1)
                   val expx = create_exps(s.expr)(x._2)
-                  get_flip(tpe(s.loc),x._1,Default) match {
+                  get_flip(s.loc.tpe,x._1,Default) match {
                      case Default => constrain(width_BANG(locx),width_BANG(expx))
                      case Flip => constrain(width_BANG(expx),width_BANG(locx)) }}
                s }
             case (s:DefRegister) => {
                constrain(width_BANG(s.reset),ONE)
                constrain(ONE,width_BANG(s.reset))
-               get_constraints_t(s.tpe,tpe(s.init),Default)
+               get_constraints_t(s.tpe,s.init.tpe,Default)
                s }
             case (s:Conditionally) => {
                v += WGeq(width_BANG(s.pred),ONE)
@@ -661,7 +661,7 @@ object ExpandConnects extends Pass {
                e map (set_gender) match {
                   case (e:WRef) => WRef(e.name,e.tpe,e.kind,genders(e.name))
                   case (e:WSubField) => {
-                     val f = get_field(tpe(e.exp),e.name)
+                     val f = get_field(e.exp.tpe,e.name)
                      val genderx = times(gender(e.exp),f.flip)
                      WSubField(e.exp,e.name,e.tpe,genderx)
                   }
@@ -677,7 +677,7 @@ object ExpandConnects extends Pass {
                case (s:DefMemory) => { genders(s.name) = MALE; s }
                case (s:DefNode) => { genders(s.name) = MALE; s }
                case (s:IsInvalid) => {
-                  val n = get_size(tpe(s.expr))
+                  val n = get_size(s.expr.tpe)
                   val invalids = ArrayBuffer[Statement]()
                   val exps = create_exps(s.expr)
                   for (i <- 0 until n) {
@@ -696,14 +696,14 @@ object ExpandConnects extends Pass {
                   } else Block(invalids)
                }
                case (s:Connect) => {
-                  val n = get_size(tpe(s.loc))
+                  val n = get_size(s.loc.tpe)
                   val connects = ArrayBuffer[Statement]()
                   val locs = create_exps(s.loc)
                   val exps = create_exps(s.expr)
                   for (i <- 0 until n) {
                      val locx = locs(i)
                      val expx = exps(i)
-                     val sx = get_flip(tpe(s.loc),i,Default) match {
+                     val sx = get_flip(s.loc.tpe,i,Default) match {
                         case Default => Connect(s.info,locx,expx)
                         case Flip => Connect(s.info,expx,locx)
                      }
@@ -712,14 +712,14 @@ object ExpandConnects extends Pass {
                   Block(connects)
                }
                case (s:PartialConnect) => {
-                  val ls = get_valid_points(tpe(s.loc),tpe(s.expr),Default,Default)
+                  val ls = get_valid_points(s.loc.tpe,s.expr.tpe,Default,Default)
                   val connects = ArrayBuffer[Statement]()
                   val locs = create_exps(s.loc)
                   val exps = create_exps(s.expr)
                   ls.foreach { x => {
                      val locx = locs(x._1)
                      val expx = exps(x._2)
-                     val sx = get_flip(tpe(s.loc),x._1,Default) match {
+                     val sx = get_flip(s.loc.tpe,x._1,Default) match {
                         case Default => Connect(s.info,locx,expx)
                         case Flip => Connect(s.info,expx,locx)
                      }
@@ -755,7 +755,7 @@ object Legalize extends Pass {
   def legalizeShiftRight (e: DoPrim): Expression = e.op match {
     case Shr => {
       val amount = e.consts(0).toInt
-      val width = long_BANG(tpe(e.args(0)))
+      val width = long_BANG(e.args(0).tpe)
       lazy val msb = width - 1
       if (amount >= width) {
         e.tpe match {
@@ -771,9 +771,9 @@ object Legalize extends Pass {
     case _ => e
   }
   def legalizeConnect(c: Connect): Statement = {
-    val t = tpe(c.loc)
+    val t = c.loc.tpe
     val w = long_BANG(t)
-    if (w >= long_BANG(tpe(c.expr))) c
+    if (w >= long_BANG(c.expr.tpe)) c
     else {
       val newType = t match {
         case _: UIntType => UIntType(IntWidth(w))
@@ -811,8 +811,8 @@ object VerilogWrap extends Pass {
             if (e.op == Tail) {
                (a0()) match {
                   case (e0:DoPrim) => {
-                     if (e0.op == Add) DoPrim(Addw,e0.args,Seq(),tpe(e))
-                     else if (e0.op == Sub) DoPrim(Subw,e0.args,Seq(),tpe(e))
+                     if (e0.op == Add) DoPrim(Addw,e0.args,Seq(),e.tpe)
+                     else if (e0.op == Sub) DoPrim(Subw,e0.args,Seq(),e.tpe)
                      else e
                   }
                   case (e0) => e
@@ -913,12 +913,12 @@ object CInferTypes extends Pass {
          def infer_types_e (e:Expression) : Expression = {
             e map infer_types_e match {
                case (e:Reference) => Reference(e.name, types.getOrElse(e.name,UnknownType))
-               case (e:SubField) => SubField(e.expr,e.name,field_type(tpe(e.expr),e.name))
-               case (e:SubIndex) => SubIndex(e.expr,e.value,sub_type(tpe(e.expr)))
-               case (e:SubAccess) => SubAccess(e.expr,e.index,sub_type(tpe(e.expr)))
+               case (e:SubField) => SubField(e.expr,e.name,field_type(e.expr.tpe,e.name))
+               case (e:SubIndex) => SubIndex(e.expr,e.value,sub_type(e.expr.tpe))
+               case (e:SubAccess) => SubAccess(e.expr,e.index,sub_type(e.expr.tpe))
                case (e:DoPrim) => set_primop_type(e)
                case (e:Mux) => Mux(e.cond,e.tval,e.fval,mux_type(e.tval,e.tval))
-               case (e:ValidIf) => ValidIf(e.cond,e.value,tpe(e.value))
+               case (e:ValidIf) => ValidIf(e.cond,e.value,e.value.tpe)
                case (_:UIntLiteral | _:SIntLiteral) => e
             }
          }
@@ -1067,8 +1067,8 @@ object RemoveCHIRRTL extends Pass {
          val e2s = create_exps(e.fval)
          (e1s,e2s).zipped map ((e1,e2) => Mux(e.cond,e1,e2,mux_type(e1,e2)))
       case (e:ValidIf) =>
-         create_exps(e.value) map (e1 => ValidIf(e.cond,e1,tpe(e1)))
-      case (e) => (tpe(e)) match {
+         create_exps(e.value) map (e1 => ValidIf(e.cond,e1,e1.tpe))
+      case (e) => (e.tpe) match {
          case (_:GroundType) => Seq(e)
          case (t:BundleType) => (t.fields foldLeft Seq[Expression]())((exps, f) =>
             exps ++ create_exps(SubField(e,f.name,f.tpe)))
@@ -1276,7 +1276,7 @@ object RemoveCHIRRTL extends Pass {
                     case Some(en) => stmts += Connect(s.info,en,one)
                   }
                   if (has_write_mport) {
-                     val ls = get_valid_points(tpe(s.loc),tpe(s.expr),Default,Default)
+                     val ls = get_valid_points(s.loc.tpe,s.expr.tpe,Default,Default)
                      val locs = create_exps(get_mask(s.loc))
                      for (x <- ls ) {
                         val locx = locs(x._1)
diff --git a/src/main/scala/firrtl/passes/SplitExpressions.scala b/src/main/scala/firrtl/passes/SplitExpressions.scala
index 1c9674e1..12d9982b 100644
--- a/src/main/scala/firrtl/passes/SplitExpressions.scala
+++ b/src/main/scala/firrtl/passes/SplitExpressions.scala
@@ -2,7 +2,7 @@ package firrtl
 package passes
 
 import firrtl.Mappers.{ExpMap, StmtMap}
-import firrtl.Utils.{tpe, kind, gender, info}
+import firrtl.Utils.{kind, gender, info}
 import firrtl.ir._
 import scala.collection.mutable
 
@@ -21,17 +21,17 @@ object SplitExpressions extends Pass {
             case e: DoPrim => {
                val name = namespace.newTemp
                v += DefNode(info(s), name, e)
-               WRef(name, tpe(e), kind(e), gender(e))
+               WRef(name, e.tpe, kind(e), gender(e))
             }
             case e: Mux => {
                val name = namespace.newTemp
                v += DefNode(info(s), name, e)
-               WRef(name, tpe(e), kind(e), gender(e))
+               WRef(name, e.tpe, kind(e), gender(e))
             }
             case e: ValidIf => {
                val name = namespace.newTemp
                v += DefNode(info(s), name, e)
-               WRef(name, tpe(e), kind(e), gender(e))
+               WRef(name, e.tpe, kind(e), gender(e))
             }
             case e => e
          }