diff options
| author | Schuyler Eldridge | 2020-06-22 18:44:54 -0400 |
|---|---|---|
| committer | GitHub | 2020-06-22 22:44:54 +0000 |
| commit | a845a11458fb0feed337d416ff45a503c7771bb3 (patch) | |
| tree | 75454fcadcca8bd7c5bd60f49c6bd76fc36fccf0 /src | |
| parent | 732d08761a97faedb878f022927c2cb429398d6f (diff) | |
Set prerequisite of -X high to MinimalHighForm (#1704)
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/scala/firrtl/stage/phases/Compiler.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/stage/phases/Compiler.scala b/src/main/scala/firrtl/stage/phases/Compiler.scala index 81b45411..d1bf9be4 100644 --- a/src/main/scala/firrtl/stage/phases/Compiler.scala +++ b/src/main/scala/firrtl/stage/phases/Compiler.scala @@ -115,7 +115,7 @@ class Compiler extends Phase with Translator[AnnotationSeq, Seq[CompilerRun]] wi private def compilerToTransforms(a: FirrtlCompiler): Seq[TransformDependency] = a match { case _: firrtl.NoneCompiler => Forms.ChirrtlForm - case _: firrtl.HighFirrtlCompiler => Forms.HighForm + case _: firrtl.HighFirrtlCompiler => Forms.MinimalHighForm case _: firrtl.MiddleFirrtlCompiler => Forms.MidForm case _: firrtl.LowFirrtlCompiler => Forms.LowForm case _: firrtl.VerilogCompiler | _: firrtl.SystemVerilogCompiler => Forms.LowFormOptimized |