Support optionally filling write mask to data width via transform input config file

3 files changed, 76 insertions, 43 deletions

diff --git a/src/main/scala/firrtl/passes/AnnotateValidMemConfigs.scala b/src/main/scala/firrtl/passes/AnnotateValidMemConfigs.scala
index a84eb7e1..a7f7703b 100644
--- a/src/main/scala/firrtl/passes/AnnotateValidMemConfigs.scala
+++ b/src/main/scala/firrtl/passes/AnnotateValidMemConfigs.scala
@@ -13,7 +13,7 @@ object CustomYAMLProtocol extends DefaultYamlProtocol {
   implicit val md = yamlFormat2(MemDimension)
   implicit val sr = yamlFormat4(SRAMRules)
   implicit val wm = yamlFormat2(WMaskArg)
-  implicit val sc = yamlFormat10(SRAMCompiler)
+  implicit val sc = yamlFormat11(SRAMCompiler)
 }
 
 case class DimensionRules(
@@ -113,7 +113,10 @@ case class SRAMCompiler(
     // config pattern
     configPattern: Option[String],
     // read documentation for details 
-    defaultArgs: Option[String]
+    defaultArgs: Option[String],
+    // default behavior (if not used) is to have wmask port width = datawidth/maskgran
+    // if true: wmask port width pre-filled to datawidth
+    fillWMask: Boolean
 ){
   require(portType == "RW" || portType == "R,W", "Memory must be single port RW or dual port R,W")
   require(
@@ -143,16 +146,19 @@ case class SRAMCompiler(
       if (validCombos.nonEmpty) validCombos.head
       else getBestAlternative(m)
     }
+    val usesMaskGran = containsInfo(m.info,"maskGran")
     if (configPattern != None) {
       val newConfig = usedConfig.serialize(configPattern.get) + "\n"
       val currentBuff = {
-        if (containsInfo(m.info,"maskGran")) maskConfigOutputBuffer 
+        if (usesMaskGran) maskConfigOutputBuffer 
         else noMaskConfigOutputBuffer
       }
       if (!currentBuff.toString.contains(newConfig))
         currentBuff.append(newConfig)
     }
-    m.copy(info = appendInfo(m.info,"sramConfig" -> usedConfig))    
+    val temp = appendInfo(m.info,"sramConfig" -> usedConfig)
+    val newInfo = if(usesMaskGran && fillWMask) appendInfo(temp,"maskGran" -> 1) else temp
+    m.copy(info = newInfo)    
   }
 
   // TODO: Should you really be splitting in 2 if, say, depth is 1 more than allowed? should be thresholded and
diff --git a/src/main/scala/firrtl/passes/MemUtils.scala b/src/main/scala/firrtl/passes/MemUtils.scala
index c606208c..97915194 100644
--- a/src/main/scala/firrtl/passes/MemUtils.scala
+++ b/src/main/scala/firrtl/passes/MemUtils.scala
@@ -61,6 +61,7 @@ object toBits {
   }
 }
 
+// TODO: make easier to understand
 object toBitMask {
   def apply(e: Expression, dataType: Type): Expression = e match {
     case ex: WRef => hiermask(ex,ex.tpe,dataType)
@@ -143,6 +144,12 @@ object MemPortUtils {
     Field("clk", Default, ClockType)
   )
 
+  def getFillWMask(mem: DefMemory) = {
+    val maskGran = getInfo(mem.info,"maskGran")
+    if (maskGran == None) false
+    else maskGran.get == 1
+  }
+
   def rPortToBundle(mem: DefMemory) = BundleType(defaultPortSeq(mem) :+ Field("data", Flip, mem.dataType))
   def rPortToFlattenBundle(mem: DefMemory) = BundleType(defaultPortSeq(mem) :+ Field("data", Flip, flattenType(mem.dataType)))
 
@@ -153,13 +160,20 @@ object MemPortUtils {
       else defaultSeq
     )
   }
+
   def wPortToFlattenBundle(mem: DefMemory) = {
     val defaultSeq = defaultPortSeq(mem) :+ Field("data", Default, flattenType(mem.dataType))
     BundleType(
-      if (containsInfo(mem.info,"maskGran")) defaultSeq :+ Field("mask", Default, flattenType(create_mask(mem.dataType)))
+      if (containsInfo(mem.info,"maskGran")) {
+        defaultSeq :+ {
+          if (getFillWMask(mem)) Field("mask", Default, flattenType(mem.dataType))
+          else Field("mask", Default, flattenType(create_mask(mem.dataType)))
+        }
+      }
       else defaultSeq
     )  
   }
+  // TODO: Don't use create_mask???
 
   def rwPortToBundle(mem: DefMemory) ={
     val defaultSeq = defaultPortSeq(mem) ++ Seq(
@@ -172,6 +186,7 @@ object MemPortUtils {
       else defaultSeq
     )
   }
+
   def rwPortToFlattenBundle(mem: DefMemory) ={
     val defaultSeq = defaultPortSeq(mem) ++ Seq(
       Field("wmode", Default, UIntType(IntWidth(1))),
@@ -179,15 +194,21 @@ object MemPortUtils {
       Field("rdata", Flip, flattenType(mem.dataType))
     )
     BundleType(
-      if (containsInfo(mem.info,"maskGran")) defaultSeq :+ Field("wmask", Default, flattenType(create_mask(mem.dataType)))
+      if (containsInfo(mem.info,"maskGran")) {
+        defaultSeq :+ {
+          if (getFillWMask(mem)) Field("wmask", Default, flattenType(mem.dataType))
+          else Field("wmask", Default, flattenType(create_mask(mem.dataType)))
+        }
+      }
       else defaultSeq
-    )
+    )  
   }
 
   def memToBundle(s: DefMemory) = BundleType(
     s.readers.map(p => Field(p, Default, rPortToBundle(s))) ++
       s.writers.map(p => Field(p, Default, wPortToBundle(s))) ++
       s.readwriters.map(p => Field(p, Default, rwPortToBundle(s))))
+  
   def memToFlattenBundle(s: DefMemory) = BundleType(
     s.readers.map(p => Field(p, Default, rPortToFlattenBundle(s))) ++
       s.writers.map(p => Field(p, Default, wPortToFlattenBundle(s))) ++
diff --git a/src/main/scala/firrtl/passes/ReplaceMemMacros.scala b/src/main/scala/firrtl/passes/ReplaceMemMacros.scala
index 8144477c..94be10e7 100644
--- a/src/main/scala/firrtl/passes/ReplaceMemMacros.scala
+++ b/src/main/scala/firrtl/passes/ReplaceMemMacros.scala
@@ -69,7 +69,6 @@ class ReplaceMemMacros(writer: ConfWriter) extends Pass {
     val stmts = ArrayBuffer[Statement]()
     val wrapperioPorts = MemPortUtils.memToBundle(m).fields.map(f => Port(NoInfo, f.name, Input, f.tpe)) 
     val bbProto = m.copy(dataType = flattenType(m.dataType))
-    //val bbioPorts = MemPortUtils.memToBundle(bbProto).fields.map(f => Port(NoInfo, f.name, Input, f.tpe)) 
     val bbioPorts = MemPortUtils.memToFlattenBundle(m).fields.map(f => Port(NoInfo, f.name, Input, f.tpe)) 
 
     stmts += WDefInstance(NoInfo,m.name,m.name,UnknownType)
@@ -92,66 +91,73 @@ class ReplaceMemMacros(writer: ConfWriter) extends Pass {
     Seq(bb,wrapper)
   }
 
-  def adaptReader(aggPort: Expression, aggMem: DefMemory, groundPort: Expression, groundMem: DefMemory) = Seq(
-    connectFields(groundPort,"addr",aggPort,"addr"),
-    connectFields(groundPort,"en",aggPort,"en"),
-    connectFields(groundPort,"clk",aggPort,"clk"),
+  // TODO: get rid of copy pasta
+  def adaptReader(wrapperPort: Expression, wrapperMem: DefMemory, bbPort: Expression, bbMem: DefMemory) = Seq(
+    connectFields(bbPort,"addr",wrapperPort,"addr"),
+    connectFields(bbPort,"en",wrapperPort,"en"),
+    connectFields(bbPort,"clk",wrapperPort,"clk"),
     fromBits(
-      WSubField(aggPort,"data",aggMem.dataType,UNKNOWNGENDER),
-      WSubField(groundPort,"data",groundMem.dataType,UNKNOWNGENDER)
+      WSubField(wrapperPort,"data",wrapperMem.dataType,UNKNOWNGENDER),
+      WSubField(bbPort,"data",bbMem.dataType,UNKNOWNGENDER)
     )
   )
 
-  def adaptWriter(aggPort: Expression, aggMem: DefMemory, groundPort: Expression, groundMem: DefMemory) = {
+  def adaptWriter(wrapperPort: Expression, wrapperMem: DefMemory, bbPort: Expression, bbMem: DefMemory) = {
     val defaultSeq = Seq(
-      connectFields(groundPort,"addr",aggPort,"addr"),
-      connectFields(groundPort,"en",aggPort,"en"),
-      connectFields(groundPort,"clk",aggPort,"clk"),
+      connectFields(bbPort,"addr",wrapperPort,"addr"),
+      connectFields(bbPort,"en",wrapperPort,"en"),
+      connectFields(bbPort,"clk",wrapperPort,"clk"),
       Connect(
         NoInfo,
-        WSubField(groundPort,"data",groundMem.dataType,UNKNOWNGENDER),
-        toBits(WSubField(aggPort,"data",aggMem.dataType,UNKNOWNGENDER))
+        WSubField(bbPort,"data",bbMem.dataType,UNKNOWNGENDER),
+        toBits(WSubField(wrapperPort,"data",wrapperMem.dataType,UNKNOWNGENDER))
       )
     )
-    if (containsInfo(aggMem.info,"maskGran")) {
-      val wrapperMask = create_mask(aggMem.dataType)
-      val bbMask = flattenType(wrapperMask)
+    if (containsInfo(wrapperMem.info,"maskGran")) {
+      val wrapperMask = create_mask(wrapperMem.dataType)
+      val fillWMask = getFillWMask(wrapperMem)
+      val bbMask = if (fillWMask) flattenType(wrapperMem.dataType) else flattenType(wrapperMask)
+      val rhs = {
+        if (fillWMask) toBitMask(WSubField(wrapperPort,"mask",wrapperMask,UNKNOWNGENDER),wrapperMem.dataType)
+        else toBits(WSubField(wrapperPort,"mask",wrapperMask,UNKNOWNGENDER))
+      }
       defaultSeq :+ Connect(
         NoInfo,
-        //WSubField(groundPort,"mask",create_mask(groundMem.dataType),UNKNOWNGENDER),
-        //toBitMask(WSubField(aggPort,"mask",create_mask(aggMem.dataType),UNKNOWNGENDER),aggMem.dataType)
-        WSubField(groundPort,"mask",bbMask,UNKNOWNGENDER),
-        toBits(WSubField(aggPort,"mask",wrapperMask,UNKNOWNGENDER))
+        WSubField(bbPort,"mask",bbMask,UNKNOWNGENDER),
+        rhs
       )
     }
     else defaultSeq
   }
 
-  def adaptReadWriter(aggPort: Expression, aggMem: DefMemory, groundPort: Expression, groundMem: DefMemory) = {
+  def adaptReadWriter(wrapperPort: Expression, wrapperMem: DefMemory, bbPort: Expression, bbMem: DefMemory) = {
     val defaultSeq = Seq(
-      connectFields(groundPort,"addr",aggPort,"addr"),
-      connectFields(groundPort,"en",aggPort,"en"),
-      connectFields(groundPort,"clk",aggPort,"clk"),
-      connectFields(groundPort,"wmode",aggPort,"wmode"),
+      connectFields(bbPort,"addr",wrapperPort,"addr"),
+      connectFields(bbPort,"en",wrapperPort,"en"),
+      connectFields(bbPort,"clk",wrapperPort,"clk"),
+      connectFields(bbPort,"wmode",wrapperPort,"wmode"),
       Connect(
         NoInfo,
-        WSubField(groundPort,"wdata",groundMem.dataType,UNKNOWNGENDER),
-        toBits(WSubField(aggPort,"wdata",aggMem.dataType,UNKNOWNGENDER))
+        WSubField(bbPort,"wdata",bbMem.dataType,UNKNOWNGENDER),
+        toBits(WSubField(wrapperPort,"wdata",wrapperMem.dataType,UNKNOWNGENDER))
       ),
       fromBits(
-        WSubField(aggPort,"rdata",aggMem.dataType,UNKNOWNGENDER),
-        WSubField(groundPort,"rdata",groundMem.dataType,UNKNOWNGENDER)
+        WSubField(wrapperPort,"rdata",wrapperMem.dataType,UNKNOWNGENDER),
+        WSubField(bbPort,"rdata",bbMem.dataType,UNKNOWNGENDER)
       )
     )
-    if (containsInfo(aggMem.info,"maskGran")){
-      val wrapperMask = create_mask(aggMem.dataType)
-      val bbMask = flattenType(wrapperMask)
+    if (containsInfo(wrapperMem.info,"maskGran")) {
+      val wrapperMask = create_mask(wrapperMem.dataType)
+      val fillWMask = getFillWMask(wrapperMem)
+      val bbMask = if (fillWMask) flattenType(wrapperMem.dataType) else flattenType(wrapperMask)
+      val rhs = {
+        if (fillWMask) toBitMask(WSubField(wrapperPort,"wmask",wrapperMask,UNKNOWNGENDER),wrapperMem.dataType)
+        else toBits(WSubField(wrapperPort,"wmask",wrapperMask,UNKNOWNGENDER))
+      }
       defaultSeq :+ Connect(
         NoInfo,
-        //WSubField(groundPort,"wmask",create_mask(groundMem.dataType),UNKNOWNGENDER),
-        //toBitMask(WSubField(aggPort,"wmask",create_mask(aggMem.dataType),UNKNOWNGENDER),aggMem.dataType)
-        WSubField(groundPort,"wmask",bbMask,UNKNOWNGENDER),
-        toBits(WSubField(aggPort,"wmask",wrapperMask,UNKNOWNGENDER))
+        WSubField(bbPort,"wmask",bbMask,UNKNOWNGENDER),
+        rhs
       )
     }
     else defaultSeq