Merge pull request #878 from seldridge/issue-764-refactor-pr-pointer-systemVerilogCompiler

[F764.3] Add explicit SystemVerilogCompiler class

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

2 files changed, 6 insertions, 1 deletions

diff --git a/src/main/scala/firrtl/ExecutionOptionsManager.scala b/src/main/scala/firrtl/ExecutionOptionsManager.scala
index bb5e68a3..1754338c 100644
--- a/src/main/scala/firrtl/ExecutionOptionsManager.scala
+++ b/src/main/scala/firrtl/ExecutionOptionsManager.scala
@@ -209,7 +209,7 @@ extends ComposableOptions {
       case "low"       => new LowFirrtlCompiler()
       case "middle"    => new MiddleFirrtlCompiler()
       case "verilog"   => new VerilogCompiler()
-      case "sverilog"  => new VerilogCompiler()
+      case "sverilog"  => new SystemVerilogCompiler()
     }
   }
 
diff --git a/src/main/scala/firrtl/LoweringCompilers.scala b/src/main/scala/firrtl/LoweringCompilers.scala
index dce6bac9..92f9a9a4 100644
--- a/src/main/scala/firrtl/LoweringCompilers.scala
+++ b/src/main/scala/firrtl/LoweringCompilers.scala
@@ -158,3 +158,8 @@ class MinimumVerilogCompiler extends Compiler {
   def transforms: Seq[Transform] = getLoweringTransforms(ChirrtlForm, LowForm) ++
     Seq(new MinimumLowFirrtlOptimization, new BlackBoxSourceHelper)
 }
+
+/** Currently just an alias for the [[VerilogCompiler]] */
+class SystemVerilogCompiler extends VerilogCompiler {
+  Driver.dramaticWarning("SystemVerilog Compiler behaves the same as the Verilog Compiler!")
+}