DCE printf and stop statements with constant-0 enables

This gets rid of about 10% of the generated Verilog in the rocket-chip
default config.

1 files changed, 7 insertions, 0 deletions

diff --git a/src/main/scala/firrtl/transforms/DeadCodeElimination.scala b/src/main/scala/firrtl/transforms/DeadCodeElimination.scala
index 8f9fad46..deb7299d 100644
--- a/src/main/scala/firrtl/transforms/DeadCodeElimination.scala
+++ b/src/main/scala/firrtl/transforms/DeadCodeElimination.scala
@@ -212,6 +212,11 @@ class DeadCodeElimination extends Transform with ResolvedAnnotationPaths with Re
     var emptyBody = true
     renames.setModule(mod.name)
 
+    def deleteIfNotEnabled(stmt: Statement, en: Expression): Statement = en match {
+      case UIntLiteral(v, _) if v == BigInt(0) => EmptyStmt
+      case _ => stmt
+    }
+
     def onStmt(stmt: Statement): Statement = {
       val stmtx = stmt match {
         case inst: WDefInstance =>
@@ -230,6 +235,8 @@ class DeadCodeElimination extends Transform with ResolvedAnnotationPaths with Re
             EmptyStmt
           }
           else decl
+        case print: Print => deleteIfNotEnabled(print, print.en)
+        case stop: Stop => deleteIfNotEnabled(stop, stop.en)
         case con: Connect =>
           val node = getDeps(con.loc) match { case Seq(elt) => elt }
           if (deadNodes.contains(node)) EmptyStmt else con