Improve RemoveReset handling of invalid inits

This modifies RemoveReset to NOT generate a mux for
invalid (IsInvalid) inits. In the case of an invalid init, the reset
is converted to a self-connect and no mux is generated.

This is implemented as a new, initial pass over the module to populate
a set of all invalid signals. During the subsequent, circuit-modifying
pass, this invalid set is queried to special case the handling of
invalid inits.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

1 files changed, 23 insertions, 1 deletions

diff --git a/src/main/scala/firrtl/transforms/RemoveReset.scala b/src/main/scala/firrtl/transforms/RemoveReset.scala
index 0b8b907d..ed1baf7d 100644
--- a/src/main/scala/firrtl/transforms/RemoveReset.scala
+++ b/src/main/scala/firrtl/transforms/RemoveReset.scala
@@ -5,8 +5,10 @@ package transforms
 
 import firrtl.ir._
 import firrtl.Mappers._
+import firrtl.traversals.Foreachers._
+import firrtl.WrappedExpression.we
 
-import scala.collection.mutable
+import scala.collection.{immutable, mutable}
 
 /** Remove Synchronous Reset
   *
@@ -18,10 +20,30 @@ class RemoveReset extends Transform {
 
   private case class Reset(cond: Expression, value: Expression)
 
+  /** Return an immutable set of all invalid expressions in a module
+    * @param m a module
+    */
+  private def computeInvalids(m: DefModule): immutable.Set[WrappedExpression] = {
+    val invalids = mutable.HashSet.empty[WrappedExpression]
+
+    def onStmt(s: Statement): Unit = s match {
+      case IsInvalid(_, expr)                                 => invalids += we(expr)
+      case Connect(_, lhs, rhs) if invalids.contains(we(rhs)) => invalids += we(lhs)
+      case other                                              => other.foreach(onStmt)
+    }
+
+    m.foreach(onStmt)
+    invalids.toSet
+  }
+
   private def onModule(m: DefModule): DefModule = {
     val resets = mutable.HashMap.empty[String, Reset]
+    val invalids = computeInvalids(m)
     def onStmt(stmt: Statement): Statement = {
       stmt match {
+        /* A register is initialized to an invalid expression */
+        case reg @ DefRegister(_, _, _, _, _, init) if invalids.contains(we(init)) =>
+          reg.copy(reset = Utils.zero, init = WRef(reg))
         case reg @ DefRegister(_, rname, _, _, reset, init)
             if reset != Utils.zero && reset.tpe != AsyncResetType =>
           // Add register reset to map