Use Vector instead of List for bulk renaming in RenameMap

3 files changed, 8 insertions, 8 deletions

diff --git a/src/main/scala/firrtl/RenameMap.scala b/src/main/scala/firrtl/RenameMap.scala
index e95260af..c41f15b9 100644
--- a/src/main/scala/firrtl/RenameMap.scala
+++ b/src/main/scala/firrtl/RenameMap.scala
@@ -308,7 +308,7 @@ final class RenameMap private () {
       case (x, Seq(y)) if x == y =>
       case _ =>
         tos.foreach{recordSensitivity(from, _)}
-        val existing = underlying.getOrElse(from, Seq.empty)
+        val existing = underlying.getOrElse(from, Vector.empty)
         val updated = existing ++ tos
         underlying(from) = updated
         getCache.clear()
diff --git a/src/main/scala/firrtl/passes/Inline.scala b/src/main/scala/firrtl/passes/Inline.scala
index d6af69c1..feda80f2 100644
--- a/src/main/scala/firrtl/passes/Inline.scala
+++ b/src/main/scala/firrtl/passes/Inline.scala
@@ -128,18 +128,18 @@ class InlineInstances extends Transform {
         val port = ComponentName(s"$ref.$field", currentModule)
         val inst = ComponentName(s"$ref", currentModule)
         (renames.get(port), renames.get(inst)) match {
-          case (Some(p :: Nil), _)              =>
+          case (Some(Seq(p)), _)              =>
             p.toTarget match {
               case ReferenceTarget(_, _, Seq(), r, Seq(TargetToken.Field(f))) => wsf.copy(expr = wr.copy(name = r), name = f)
               case ReferenceTarget(_, _, Seq(), r, Seq()) => WRef(r, tpe, WireKind, gen)
             }
-          case (None,           Some(i :: Nil)) => wsf.map(appendRefPrefix(currentModule, renames))
+          case (None,           Some(Seq(i))) => wsf.map(appendRefPrefix(currentModule, renames))
           case (None,           None)           => wsf
         }
       case wr@ WRef(name, _, _, _) =>
         val comp = ComponentName(name, currentModule)
         renames.get(comp).orElse(Some(Seq(comp))) match {
-          case Some(car :: Nil) => wr.copy(name=car.name)
+          case Some(Seq(car)) => wr.copy(name=car.name)
           case c@ Some(_)       => throw new PassException(
             s"Inlining found mlutiple renames for ref $comp -> $c. This should be impossible...")
         }
diff --git a/src/main/scala/firrtl/transforms/RemoveKeywordCollisions.scala b/src/main/scala/firrtl/transforms/RemoveKeywordCollisions.scala
index 05fd0228..66e39e53 100644
--- a/src/main/scala/firrtl/transforms/RemoveKeywordCollisions.scala
+++ b/src/main/scala/firrtl/transforms/RemoveKeywordCollisions.scala
@@ -65,9 +65,9 @@ class RemoveKeywordCollisions(keywords: Set[String]) extends Transform {
     }
 
     namedx match {
-      case ComponentName(n, _) :: Nil => n
-      case ModuleName(n, _)    :: Nil => n
-      case CircuitName(n)      :: Nil => n
+      case Seq(ComponentName(n, _)) => n
+      case Seq(ModuleName(n, _))    => n
+      case Seq(CircuitName(n))      => n
       case x => throw new PassException(
         s"Verilog renaming shouldn't result in multiple renames, but found '$named -> $namedx'")
     }
@@ -189,7 +189,7 @@ class RemoveKeywordCollisions(keywords: Set[String]) extends Transform {
 
     // Rename the circuit if the top module was renamed
     val mainx = renames.get(ModuleName(c.main, CircuitName(c.main))) match {
-      case Some(ModuleName(m, _) :: Nil) =>
+      case Some(Seq(ModuleName(m, _))) =>
         renames.rename(CircuitName(c.main), CircuitName(m))
         m
       case x@ Some(_) => throw new PassException(