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authorSchuyler Eldridge2020-06-17 17:15:47 -0400
committerSchuyler Eldridge2020-06-25 13:46:23 -0400
commit862ae2131a80d6a84423b17242612133f9ddec59 (patch)
tree47d2bcf9ecb71df35c19bf7b65a34a4c709fcb50 /src
parent305e9da16392f5ce8c3532469eea271c1d0b6654 (diff)
Test ManipulateNamesAllowlistResultAnnotation
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Diffstat (limited to 'src')
-rw-r--r--src/test/scala/firrtlTests/transforms/ManipulateNamesSpec.scala57
1 files changed, 55 insertions, 2 deletions
diff --git a/src/test/scala/firrtlTests/transforms/ManipulateNamesSpec.scala b/src/test/scala/firrtlTests/transforms/ManipulateNamesSpec.scala
index 82cc997d..b1e2eeb9 100644
--- a/src/test/scala/firrtlTests/transforms/ManipulateNamesSpec.scala
+++ b/src/test/scala/firrtlTests/transforms/ManipulateNamesSpec.scala
@@ -2,14 +2,22 @@
package firrtlTests.transforms
-import firrtl.{ir, CircuitState, FirrtlUserException, Namespace, Parser}
+import firrtl.{
+ ir,
+ CircuitState,
+ FirrtlUserException,
+ Namespace,
+ Parser,
+ RenameMap
+}
import firrtl.annotations.CircuitTarget
import firrtl.options.Dependency
import firrtl.testutils.FirrtlCheckers._
import firrtl.transforms.{
ManipulateNames,
ManipulateNamesBlocklistAnnotation,
- ManipulateNamesAllowlistAnnotation
+ ManipulateNamesAllowlistAnnotation,
+ ManipulateNamesAllowlistResultAnnotation
}
import org.scalatest.flatspec.AnyFlatSpec
@@ -173,4 +181,49 @@ class ManipulateNamesSpec extends AnyFlatSpec with Matchers {
}
}
+ behavior of "ManipulateNamesAllowlistResultAnnotation"
+
+ it should "delete itself if the new target is deleted" in {
+ val `~Foo|Bar` = CircuitTarget("Foo").module("Bar")
+ val `~Foo|prefix_Bar` = CircuitTarget("Foo").module("prefix_Bar")
+
+ val a = ManipulateNamesAllowlistResultAnnotation(
+ targets = Seq(Seq(`~Foo|prefix_Bar`)),
+ transform = Dependency[AddPrefix],
+ oldTargets = Seq(Seq(`~Foo|Bar`))
+ )
+
+ val r = RenameMap()
+ r.delete(`~Foo|prefix_Bar`)
+
+ a.update(r) should be (empty)
+ }
+
+ it should "drop a deleted target" in {
+ val `~Foo|Bar` = CircuitTarget("Foo").module("Bar")
+ val `~Foo|prefix_Bar` = CircuitTarget("Foo").module("prefix_Bar")
+ val `~Foo|Baz` = CircuitTarget("Foo").module("Baz")
+ val `~Foo|prefix_Baz` = CircuitTarget("Foo").module("prefix_Baz")
+
+ val a = ManipulateNamesAllowlistResultAnnotation(
+ targets = Seq(Seq(`~Foo|prefix_Bar`), Seq(`~Foo|prefix_Baz`)),
+ transform = Dependency[AddPrefix],
+ oldTargets = Seq(Seq(`~Foo|Bar`), Seq(`~Foo|Baz`))
+ )
+
+ val r = RenameMap()
+ r.delete(`~Foo|prefix_Bar`)
+
+ val ax = a.update(r).collect {
+ case b: ManipulateNamesAllowlistResultAnnotation[_] => b
+ }
+
+ ax should not be length (1)
+
+ val keys = ax.head.toRenameMap.getUnderlying.keys
+
+ keys should not contain (`~Foo|Bar`)
+ keys should contain (`~Foo|Baz`)
+ }
+
}