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authorjackkoenig2016-09-12 21:12:35 -0700
committerjackkoenig2016-09-12 21:30:36 -0700
commit7f12a07d941bd08749ef350654fe9a324b882a6b (patch)
treefe66e9839a79ce4b08755f7ad9947e15e48ae0bf /src
parent117d82b38cc49c53422fe77e5c697792faaa6486 (diff)
Change bitWidth to support ClockType
Match on GroundType instead of UIntType and SIntType
Diffstat (limited to 'src')
-rw-r--r--src/main/scala/firrtl/passes/MemUtils.scala3
1 files changed, 1 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/passes/MemUtils.scala b/src/main/scala/firrtl/passes/MemUtils.scala
index b235213a..adbf23e5 100644
--- a/src/main/scala/firrtl/passes/MemUtils.scala
+++ b/src/main/scala/firrtl/passes/MemUtils.scala
@@ -83,8 +83,7 @@ object bitWidth {
def widthOf(dt: Type): BigInt = dt match {
case t: VectorType => t.size * bitWidth(t.tpe)
case t: BundleType => t.fields.map(f => bitWidth(f.tpe)).foldLeft(BigInt(0))(_+_)
- case UIntType(IntWidth(width)) => width
- case SIntType(IntWidth(width)) => width
+ case GroundType(IntWidth(width)) => width
case t => error("Unknown type encountered in bitWidth!")
}
}