use case object for Kind (#267)

use case object for Kind

13 files changed, 41 insertions, 43 deletions

diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala
index 0af002b2..85955088 100644
--- a/src/main/scala/firrtl/Emitter.scala
+++ b/src/main/scala/firrtl/Emitter.scala
@@ -85,11 +85,11 @@ class VerilogEmitter extends Emitter {
     else DoPrim(Eq, Seq(e.e1, zero), Nil, UIntType(IntWidth(1)))
   }
 
-  def wref(n: String, t: Type) = WRef(n, t, ExpKind(), UNKNOWNGENDER)
+  def wref(n: String, t: Type) = WRef(n, t, ExpKind, UNKNOWNGENDER)
   def remove_root(ex: Expression): Expression = ex match {
     case ex: WSubField => ex.exp match {
       case (e: WSubField) => remove_root(e)
-      case (_: WRef) => WRef(ex.name, ex.tpe, InstanceKind(), UNKNOWNGENDER)
+      case (_: WRef) => WRef(ex.name, ex.tpe, InstanceKind, UNKNOWNGENDER)
     }
     case _ => error("Shouldn't be here")
   }
@@ -261,7 +261,7 @@ class VerilogEmitter extends Emitter {
           simlist += s
           s
         case (s: DefNode) =>
-          val e = WRef(s.name, s.value.tpe, NodeKind(), MALE)
+          val e = WRef(s.name, s.value.tpe, NodeKind, MALE)
           netlist(e) = s.value
           s
         case (s) => s
@@ -434,7 +434,7 @@ class VerilogEmitter extends Emitter {
             portdefs += Seq(p.direction, "  ", p.tpe, " ", p.name)
           case Output =>
             portdefs += Seq(p.direction, " ", p.tpe, " ", p.name)
-            val ex = WRef(p.name, p.tpe, PortKind(), FEMALE)
+            val ex = WRef(p.name, p.tpe, PortKind, FEMALE)
             assign(ex, netlist(ex))
         }
       }
@@ -458,7 +458,7 @@ class VerilogEmitter extends Emitter {
           s
         case (s: DefNode) =>
           declare("wire", s.name, s.value.tpe)
-          assign(WRef(s.name, s.value.tpe, NodeKind(), MALE), s.value)
+          assign(WRef(s.name, s.value.tpe, NodeKind, MALE), s.value)
           s
         case (s: Stop) =>
           val errorString = StringLit(s"${s.ret}\n".getBytes)
@@ -468,12 +468,11 @@ class VerilogEmitter extends Emitter {
           simulate(s.clk, s.en, printf(s.string, s.args), Some("PRINTF_COND"))
           s
         case (s: WDefInstance) =>
-          val es = create_exps(WRef(s.name, s.tpe, InstanceKind(), MALE))
+          val es = create_exps(WRef(s.name, s.tpe, InstanceKind, MALE))
           instantiate(s.name, s.module, es)
           s
         case (s: DefMemory) =>
-          val mem = WRef(s.name, MemPortUtils.memType(s),
-            MemKind(s.readers ++ s.writers ++ s.readwriters), UNKNOWNGENDER)
+          val mem = WRef(s.name, MemPortUtils.memType(s), MemKind, UNKNOWNGENDER)
           def mem_exp (p: String, f: String) = {
             val t1 = field_type(mem.tpe, p)
             val t2 = field_type(t1, f)
diff --git a/src/main/scala/firrtl/Utils.scala b/src/main/scala/firrtl/Utils.scala
index d9c74840..be4700e3 100644
--- a/src/main/scala/firrtl/Utils.scala
+++ b/src/main/scala/firrtl/Utils.scala
@@ -100,7 +100,7 @@ object Utils extends LazyLogging {
   }
 
   def create_exps(n: String, t: Type): Seq[Expression] =
-    create_exps(WRef(n, t, ExpKind(), UNKNOWNGENDER))
+    create_exps(WRef(n, t, ExpKind, UNKNOWNGENDER))
   def create_exps(e: Expression): Seq[Expression] = e match {
     case (e: Mux) =>
       val e1s = create_exps(e.tval)
@@ -325,7 +325,7 @@ object Utils extends LazyLogging {
     case e: WSubField => kind(e.exp)
     case e: WSubIndex => kind(e.exp)
     case e: WSubAccess => kind(e.exp)
-    case e => ExpKind()
+    case e => ExpKind
   }
   def gender(e: Expression): Gender = e match {
     case e: WRef => e.gender
diff --git a/src/main/scala/firrtl/WIR.scala b/src/main/scala/firrtl/WIR.scala
index 9ff48446..9c63360c 100644
--- a/src/main/scala/firrtl/WIR.scala
+++ b/src/main/scala/firrtl/WIR.scala
@@ -34,14 +34,14 @@ import WrappedExpression._
 import WrappedWidth._
 
 trait Kind
-case class WireKind() extends Kind
-case class PoisonKind() extends Kind 
-case class RegKind() extends Kind
-case class InstanceKind() extends Kind
-case class PortKind() extends Kind
-case class NodeKind() extends Kind
-case class MemKind(ports: Seq[String]) extends Kind
-case class ExpKind() extends Kind
+case object WireKind extends Kind
+case object PoisonKind extends Kind
+case object RegKind extends Kind
+case object InstanceKind extends Kind
+case object PortKind extends Kind
+case object NodeKind extends Kind
+case object MemKind extends Kind
+case object ExpKind extends Kind
 
 trait Gender
 case object MALE extends Gender
diff --git a/src/main/scala/firrtl/passes/CheckInitialization.scala b/src/main/scala/firrtl/passes/CheckInitialization.scala
index 69629bf0..f90ee277 100644
--- a/src/main/scala/firrtl/passes/CheckInitialization.scala
+++ b/src/main/scala/firrtl/passes/CheckInitialization.scala
@@ -92,7 +92,7 @@ object CheckInitialization extends Pass {
           case node: DefNode =>
             val (hasVoid, voidDeps) = hasVoidExpr(node.value)
             if (hasVoid) {
-              val nodeRef = WRef(node.name, node.value.tpe, NodeKind(), MALE)
+              val nodeRef = WRef(node.name, node.value.tpe, NodeKind, MALE)
               voidExprs(nodeRef) = VoidExpr(node, voidDeps)
             }
             node
diff --git a/src/main/scala/firrtl/passes/Checks.scala b/src/main/scala/firrtl/passes/Checks.scala
index c300f7c7..3ee97d08 100644
--- a/src/main/scala/firrtl/passes/Checks.scala
+++ b/src/main/scala/firrtl/passes/Checks.scala
@@ -469,7 +469,7 @@ object CheckGenders extends Pass {
         case (MALE, FEMALE) =>
           errors append new WrongGender(info, mname, e.serialize, desired, gender)
         case (FEMALE, MALE) => kind(e) match {
-          case _: PortKind | _: InstanceKind if !flip_q(e.tpe) => // OK!
+          case PortKind | InstanceKind if !flip_q(e.tpe) => // OK!
           case _ =>
             errors append new WrongGender(info, mname, e.serialize, desired, gender)
         }
diff --git a/src/main/scala/firrtl/passes/ExpandWhens.scala b/src/main/scala/firrtl/passes/ExpandWhens.scala
index 5a7a7bac..6bd4bffd 100644
--- a/src/main/scala/firrtl/passes/ExpandWhens.scala
+++ b/src/main/scala/firrtl/passes/ExpandWhens.scala
@@ -53,7 +53,7 @@ object ExpandWhens extends Pass {
   // ========== Expand When Utilz ==========
   private def getFemaleRefs(n: String, t: Type, g: Gender): Seq[Expression] = {
     def getGender(t: Type, i: Int, g: Gender): Gender = times(g, get_flip(t, i, Default))
-    val exps = create_exps(WRef(n, t, ExpKind(), g))
+    val exps = create_exps(WRef(n, t, ExpKind, g))
     (exps.zipWithIndex foldLeft Seq[Expression]()){
       case (expsx, (exp, j)) => getGender(t, j, g) match {
         case (BIGENDER | FEMALE) => expsx :+ exp
@@ -140,12 +140,12 @@ object ExpandWhens extends Pass {
             res match {
               case _: ValidIf | _: Mux | _: DoPrim => nodes get res match {
                 case Some(name) =>
-                  netlist(lvalue) = WRef(name, res.tpe, NodeKind(), MALE)
+                  netlist(lvalue) = WRef(name, res.tpe, NodeKind, MALE)
                   EmptyStmt
                 case None =>
                   val name = namespace.newTemp
                   nodes(res) = name
-                  netlist(lvalue) = WRef(name, res.tpe, NodeKind(), MALE)
+                  netlist(lvalue) = WRef(name, res.tpe, NodeKind, MALE)
                   DefNode(s.info, name, res)
               }
               case _ =>
diff --git a/src/main/scala/firrtl/passes/InferReadWrite.scala b/src/main/scala/firrtl/passes/InferReadWrite.scala
index 664b3dfc..9fbd6ab3 100644
--- a/src/main/scala/firrtl/passes/InferReadWrite.scala
+++ b/src/main/scala/firrtl/passes/InferReadWrite.scala
@@ -128,7 +128,7 @@ object InferReadWritePass extends Pass {
                 newName = s"rw_$idx"
                 if !allPorts(newName)
               } yield newName).head
-            val rw_exp = WSubField(WRef(mem.name, ut, NodeKind(), ug), rw, ut, ug)
+            val rw_exp = WSubField(WRef(mem.name, ut, MemKind, ug), rw, ut, ug)
             readwriters += rw
             readers += r
             writers += w
@@ -142,7 +142,7 @@ object InferReadWritePass extends Pass {
             repl(s"${mem.name}.$w.data") = WSubField(rw_exp, "wdata", mem.dataType, FEMALE)
             repl(s"${mem.name}.$w.mask") = WSubField(rw_exp, "wmask", ut, FEMALE)
             stmts += Connect(NoInfo, WSubField(rw_exp, "clk", ClockType, FEMALE),
-              WRef("clk", ClockType, NodeKind(), MALE))
+              WRef("clk", ClockType, NodeKind, MALE))
             stmts += Connect(NoInfo, WSubField(rw_exp, "en", bt, FEMALE),
               DoPrim(Or, List(connects(s"${mem.name}.$r.en"), connects(s"${mem.name}.$w.en")), Nil, bt))
             stmts += Connect(NoInfo, WSubField(rw_exp, "addr", ut, FEMALE),
diff --git a/src/main/scala/firrtl/passes/Inline.scala b/src/main/scala/firrtl/passes/Inline.scala
index 43c0ef1e..12dfb497 100644
--- a/src/main/scala/firrtl/passes/Inline.scala
+++ b/src/main/scala/firrtl/passes/Inline.scala
@@ -106,7 +106,7 @@ class InlineInstances (transID: TransID) extends Transform {
                if (inlinedInstances.contains(ref)) {
                   val newName = ref + inlineDelim + field
                   set(ComponentName(ref, ModuleName(m.name, cname)), Seq.empty)
-                  WRef(newName, tpe, WireKind(), gen)
+                  WRef(newName, tpe, WireKind, gen)
                }
                else e
             }
diff --git a/src/main/scala/firrtl/passes/LowerTypes.scala b/src/main/scala/firrtl/passes/LowerTypes.scala
index b3969bea..967b4a1c 100644
--- a/src/main/scala/firrtl/passes/LowerTypes.scala
+++ b/src/main/scala/firrtl/passes/LowerTypes.scala
@@ -120,11 +120,11 @@ object LowerTypes extends Pass {
       info: Info, mname: String)(e: Expression): Expression = e match {
     case e: WRef => e
     case (_: WSubField | _: WSubIndex) => kind(e) match {
-      case k: InstanceKind =>
+      case InstanceKind =>
         val (root, tail) = splitRef(e)
         val name = loweredName(tail)
         WSubField(root, name, e.tpe, gender(e))
-      case k: MemKind =>
+      case MemKind =>
         val exps = lowerTypesMemExp(memDataTypeMap, info, mname)(e)
         exps.size match {
           case 1 => exps.head
@@ -163,7 +163,7 @@ object LowerTypes extends Pass {
       case s: WDefInstance => s.tpe match {
         case t: BundleType =>
           val fieldsx = t.fields flatMap (f =>
-            create_exps(WRef(f.name, f.tpe, ExpKind(), times(f.flip, MALE))) map (
+            create_exps(WRef(f.name, f.tpe, ExpKind, times(f.flip, MALE))) map (
               // Flip because inst genders are reversed from Module type
               e => Field(loweredName(e), swap(to_flip(gender(e))), e.tpe)))
           WDefInstance(s.info, s.name, s.module, BundleType(fieldsx))
@@ -188,12 +188,12 @@ object LowerTypes extends Pass {
         val exps = create_exps(s.value) map lowerTypesExp(memDataTypeMap, info, mname)
         Block(names zip exps map { case (n, e) => DefNode(info, loweredName(n), e) })
       case s: IsInvalid => kind(s.expr) match {
-        case _: MemKind =>
+        case MemKind =>
           Block(lowerTypesMemExp(memDataTypeMap, info, mname)(s.expr) map (IsInvalid(info, _)))
         case _ => s map lowerTypesExp(memDataTypeMap, info, mname)
       }
       case s: Connect => kind(s.loc) match {
-        case k: MemKind =>
+        case MemKind =>
           val exp = lowerTypesExp(memDataTypeMap, info, mname)(s.expr)
           val locs = lowerTypesMemExp(memDataTypeMap, info, mname)(s.loc)
           Block(locs map (Connect(info, _, exp)))
@@ -207,7 +207,7 @@ object LowerTypes extends Pass {
     val memDataTypeMap = new MemDataTypeMap
     // Lower Ports
     val portsx = m.ports flatMap { p =>
-      val exps = create_exps(WRef(p.name, p.tpe, PortKind(), to_gender(p.direction)))
+      val exps = create_exps(WRef(p.name, p.tpe, PortKind, to_gender(p.direction)))
       exps map (e => Port(p.info, loweredName(e), to_dir(gender(e)), e.tpe))
     }
     m match {
diff --git a/src/main/scala/firrtl/passes/MemUtils.scala b/src/main/scala/firrtl/passes/MemUtils.scala
index 57a7120b..21884661 100644
--- a/src/main/scala/firrtl/passes/MemUtils.scala
+++ b/src/main/scala/firrtl/passes/MemUtils.scala
@@ -229,9 +229,8 @@ object MemPortUtils {
       (mem.readwriters map (Field(_, Flip, rwType))))
   }
 
-  def kind(s: DefMemory) = MemKind(s.readers ++ s.writers ++ s.readwriters)
   def memPortField(s: DefMemory, p: String, f: String) = {
-    val mem = WRef(s.name, memType(s), kind(s), UNKNOWNGENDER)
+    val mem = WRef(s.name, memType(s), MemKind, UNKNOWNGENDER)
     val t1 = field_type(mem.tpe, p)
     val t2 = field_type(t1, f)
     WSubField(WSubField(mem, p, t1, UNKNOWNGENDER), f, t2, UNKNOWNGENDER)
diff --git a/src/main/scala/firrtl/passes/Passes.scala b/src/main/scala/firrtl/passes/Passes.scala
index 965ae339..9057c60d 100644
--- a/src/main/scala/firrtl/passes/Passes.scala
+++ b/src/main/scala/firrtl/passes/Passes.scala
@@ -59,8 +59,8 @@ class Errors {
 object ToWorkingIR extends Pass {
   def name = "Working IR"
 
-  def toExp(e:Expression) : Expression = e map (toExp) match {
-    case e: Reference => WRef(e.name, e.tpe, NodeKind(), UNKNOWNGENDER)
+  def toExp(e: Expression): Expression = e map (toExp) match {
+    case e: Reference => WRef(e.name, e.tpe, NodeKind, UNKNOWNGENDER)
     case e: SubField => WSubField(e.expr, e.name, e.tpe, UNKNOWNGENDER)
     case e: SubIndex => WSubIndex(e.expr, e.value, e.tpe, UNKNOWNGENDER)
     case e: SubAccess => WSubAccess(e.expr, e.index, e.tpe, UNKNOWNGENDER)
diff --git a/src/main/scala/firrtl/passes/Resolves.scala b/src/main/scala/firrtl/passes/Resolves.scala
index 3100f0c3..616e30f3 100644
--- a/src/main/scala/firrtl/passes/Resolves.scala
+++ b/src/main/scala/firrtl/passes/Resolves.scala
@@ -36,16 +36,16 @@ object ResolveKinds extends Pass {
   type KindMap = collection.mutable.LinkedHashMap[String, Kind]
 
   def find_port(kinds: KindMap)(p: Port): Port = {
-    kinds(p.name) = PortKind() ; p
+    kinds(p.name) = PortKind ; p
   }
 
   def find_stmt(kinds: KindMap)(s: Statement):Statement = {
     s match {
-      case s: DefWire => kinds(s.name) = WireKind()
-      case s: DefNode => kinds(s.name) = NodeKind()
-      case s: DefRegister => kinds(s.name) = RegKind()
-      case s: WDefInstance => kinds(s.name) = InstanceKind()
-      case s: DefMemory => kinds(s.name) = MemKind(s.readers ++ s.writers ++ s.readwriters)
+      case s: DefWire => kinds(s.name) = WireKind
+      case s: DefNode => kinds(s.name) = NodeKind
+      case s: DefRegister => kinds(s.name) = RegKind
+      case s: WDefInstance => kinds(s.name) = InstanceKind
+      case s: DefMemory => kinds(s.name) = MemKind
       case s =>
     } 
     s map find_stmt(kinds)
diff --git a/src/main/scala/firrtl/passes/UpdateDuplicateMemMacros.scala b/src/main/scala/firrtl/passes/UpdateDuplicateMemMacros.scala
index 81684d90..0098fa5f 100644
--- a/src/main/scala/firrtl/passes/UpdateDuplicateMemMacros.scala
+++ b/src/main/scala/firrtl/passes/UpdateDuplicateMemMacros.scala
@@ -12,7 +12,7 @@ import firrtl.Utils._
 
 object MemTransformUtils {
 
-  def createRef(n: String) = WRef(n, UnknownType, ExpKind(), UNKNOWNGENDER)
+  def createRef(n: String) = WRef(n, UnknownType, ExpKind, UNKNOWNGENDER)
   def createSubField(exp: Expression, n: String) = WSubField(exp, n, UnknownType, UNKNOWNGENDER)
   def connectFields(lref: Expression, lname: String, rref: Expression, rname: String) = 
     Connect(NoInfo, createSubField(lref, lname), createSubField(rref, rname))