Merge pull request #417 from grebe/fixedMemFix

Add FixedType to uniqueify match statement.

2 files changed, 57 insertions, 1 deletions

diff --git a/src/main/scala/firrtl/passes/Uniquify.scala b/src/main/scala/firrtl/passes/Uniquify.scala
index ab48ae6d..40783e21 100644
--- a/src/main/scala/firrtl/passes/Uniquify.scala
+++ b/src/main/scala/firrtl/passes/Uniquify.scala
@@ -203,7 +203,7 @@ object Uniquify extends Pass {
       case sx: DefRegister => Seq(Field(sx.name, Default, sx.tpe))
       case sx: WDefInstance => Seq(Field(sx.name, Default, sx.tpe))
       case sx: DefMemory => sx.dataType match {
-        case (_: UIntType | _: SIntType) =>
+        case (_: UIntType | _: SIntType | _: FixedType) =>
           Seq(Field(sx.name, Default, memType(sx)))
         case tpe: BundleType =>
           val newFields = tpe.fields map ( f =>
diff --git a/src/test/scala/firrtlTests/fixed/FixedTypeInferenceSpec.scala b/src/test/scala/firrtlTests/fixed/FixedTypeInferenceSpec.scala
index 2750ee71..d567a6da 100644
--- a/src/test/scala/firrtlTests/fixed/FixedTypeInferenceSpec.scala
+++ b/src/test/scala/firrtlTests/fixed/FixedTypeInferenceSpec.scala
@@ -3,6 +3,7 @@
 package firrtlTests
 package fixed
 
+import java.io._
 import firrtl._
 import firrtl.ir.Circuit
 import firrtl.passes._
@@ -19,6 +20,14 @@ class FixedTypeInferenceSpec extends FirrtlFlatSpec {
       lines should contain(e)
     }
   }
+  private def executeTest(input: String, expected: Seq[String], compiler: Compiler) = {
+    val writer = new StringWriter()
+    compiler.compile(CircuitState(parse(input), ChirrtlForm), writer)
+    val lines = writer.toString().split("\n") map normalized
+    expected foreach { e =>
+      lines should contain(e)
+    }
+  }
 
   "Fixed types" should "infer add correctly" in {
     val passes = Seq(
@@ -287,5 +296,52 @@ class FixedTypeInferenceSpec extends FirrtlFlatSpec {
       """.stripMargin
     executeTest(input, check.split("\n") map normalized, passes)
   }
+  "Fixed types" should "work with mems" in {
+    def input(memType: String): String =
+      s"""
+        |circuit Unit :
+        |  module Unit :
+        |    input clock : Clock
+        |    input in : Fixed<16><<8>>
+        |    input ridx : UInt<3>
+        |    output out : Fixed<16><<8>>
+        |    input widx : UInt<3>
+        |    $memType mem : Fixed<16><<8>>[8]
+        |    infer mport min = mem[ridx], clock
+        |    min <= in
+        |    infer mport mout = mem[widx], clock
+        |    out <= mout
+      """.stripMargin
+    def check(readLatency: Int, moutEn: Int, minEn: Int): String =
+      s"""
+        |circuit Unit :
+        |  module Unit :
+        |    input clock : Clock
+        |    input in : SInt<16>
+        |    input ridx : UInt<3>
+        |    output out : SInt<16>
+        |    input widx : UInt<3>
+        |
+        |    mem mem :
+        |      data-type => SInt<16>
+        |      depth => 8
+        |      read-latency => $readLatency
+        |      write-latency => 1
+        |      reader => mout
+        |      writer => min
+        |      read-under-write => undefined
+        |    out <= mem.mout.data
+        |    mem.mout.addr <= widx
+        |    mem.mout.en <= UInt<1>("h$moutEn")
+        |    mem.mout.clk <= clock
+        |    mem.min.addr <= ridx
+        |    mem.min.en <= UInt<1>("h$minEn")
+        |    mem.min.clk <= clock
+        |    mem.min.data <= in
+        |    mem.min.mask <= UInt<1>("h1")
+      """.stripMargin
+    executeTest(input("smem"), check(1, 0, 1).split("\n") map normalized, new LowFirrtlCompiler)
+    executeTest(input("cmem"), check(0, 1, 1).split("\n") map normalized, new LowFirrtlCompiler)
+  }
 }