Implement NoCommonSubexpressionElimination (#2291)

* implement NoCommonSubexpressionElimination to resolve chipsalliance/chisel3#2006

* Update src/main/scala/firrtl/passes/CommonSubexpressionElimination.scala

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

2 files changed, 26 insertions, 11 deletions

diff --git a/src/main/scala/firrtl/passes/CommonSubexpressionElimination.scala b/src/main/scala/firrtl/passes/CommonSubexpressionElimination.scala
index 70da011e..ee426c92 100644
--- a/src/main/scala/firrtl/passes/CommonSubexpressionElimination.scala
+++ b/src/main/scala/firrtl/passes/CommonSubexpressionElimination.scala
@@ -2,12 +2,16 @@
 
 package firrtl.passes
 
+import firrtl.Mappers._
 import firrtl._
+import firrtl.annotations.NoTargetAnnotation
 import firrtl.ir._
-import firrtl.Mappers._
-import firrtl.options.Dependency
+import firrtl.options.{Dependency, HasShellOptions, RegisteredTransform, ShellOption}
+
+/** Indicate that CommonSubexpressionElimination should not be run */
+case object NoCommonSubexpressionElimination extends NoTargetAnnotation
 
-object CommonSubexpressionElimination extends Pass {
+object CommonSubexpressionElimination extends Transform with HasShellOptions with DependencyAPIMigration {
 
   override def prerequisites = firrtl.stage.Forms.LowForm
   override def optionalPrerequisiteOf =
@@ -15,6 +19,14 @@ object CommonSubexpressionElimination extends Pass {
 
   override def invalidates(a: Transform) = false
 
+  val options = Seq(
+    new ShellOption[Unit](
+      longOption = "no-cse",
+      toAnnotationSeq = _ => Seq(NoCommonSubexpressionElimination),
+      helpText = "Disable common subexpression elimination"
+    )
+  )
+
   private def cse(s: Statement): Statement = {
     val expressions = collection.mutable.HashMap[MemoizedHash[Expression], String]()
     val nodes = collection.mutable.HashMap[String, Expression]()
@@ -46,11 +58,12 @@ object CommonSubexpressionElimination extends Pass {
     eliminateNodeRefs(s)
   }
 
-  def run(c: Circuit): Circuit = {
-    val modulesx = c.modules.map {
-      case m: ExtModule => m
-      case m: Module    => Module(m.info, m.name, m.ports, cse(m.body))
-    }
-    Circuit(c.info, modulesx, c.main)
-  }
+  override def execute(state: CircuitState): CircuitState =
+    if (state.annotations.contains(NoCommonSubexpressionElimination))
+      state
+    else
+      state.copy(circuit = state.circuit.copy(modules = state.circuit.modules.map({
+        case m: ExtModule => m
+        case m: Module    => Module(m.info, m.name, m.ports, cse(m.body))
+      })))
 }
diff --git a/src/main/scala/firrtl/stage/FirrtlCli.scala b/src/main/scala/firrtl/stage/FirrtlCli.scala
index 8f84ff18..abba0c66 100644
--- a/src/main/scala/firrtl/stage/FirrtlCli.scala
+++ b/src/main/scala/firrtl/stage/FirrtlCli.scala
@@ -3,6 +3,7 @@
 package firrtl.stage
 
 import firrtl.options.Shell
+import firrtl.passes.CommonSubexpressionElimination
 import firrtl.transforms.NoCircuitDedupAnnotation
 
 /** [[firrtl.options.Shell Shell]] mixin that provides command line options for FIRRTL. This does not include any
@@ -24,7 +25,8 @@ trait FirrtlCli { this: Shell =>
     PrettyNoExprInlining,
     DisableFold,
     OptimizeForFPGA,
-    CurrentFirrtlStateAnnotation
+    CurrentFirrtlStateAnnotation,
+    CommonSubexpressionElimination
   )
     .map(_.addOptions(parser))