diff options
| author | Patrick Li | 2015-04-10 15:03:07 -0700 |
|---|---|---|
| committer | Patrick Li | 2015-04-10 15:03:07 -0700 |
| commit | 5d9f23db98f003b14cc4f47b7c92c414131b780f (patch) | |
| tree | 07ed3675f5668a97004df53ded9da70c6fbb0f95 /src | |
| parent | 64a37e456519af4473592c791f269d72b008bd17 (diff) | |
Updated Stanza
Diffstat (limited to 'src')
| -rw-r--r-- | src/lib/stanza.zip | bin | 3642327 -> 3758011 bytes | |||
| -rw-r--r-- | src/main/stanza/firrtl-ir.stanza | 16 | ||||
| -rw-r--r-- | src/main/stanza/firrtl-main.stanza | 30 | ||||
| -rw-r--r-- | src/main/stanza/firrtl-test-main.stanza | 30 | ||||
| -rw-r--r-- | src/main/stanza/ir-parser.stanza | 161 | ||||
| -rw-r--r-- | src/main/stanza/ir-utils.stanza | 4 | ||||
| -rw-r--r-- | src/main/stanza/passes.stanza | 26 | ||||
| -rw-r--r-- | src/main/stanza/widthsolver.stanza | 10 |
8 files changed, 111 insertions, 166 deletions
diff --git a/src/lib/stanza.zip b/src/lib/stanza.zip Binary files differindex 85d8c9e2..fb9ac7d7 100644 --- a/src/lib/stanza.zip +++ b/src/lib/stanza.zip diff --git a/src/main/stanza/firrtl-ir.stanza b/src/main/stanza/firrtl-ir.stanza index f10dba0c..402409c0 100644 --- a/src/main/stanza/firrtl-ir.stanza +++ b/src/main/stanza/firrtl-ir.stanza @@ -1,4 +1,4 @@ -defpackage firrtl.ir2 : +defpackage firrtl/ir2 : import core import verse @@ -117,15 +117,15 @@ public defmulti type (e:Expression) -> Type public defstruct Ref <: Expression : name: Symbol - type: Type [multi => false] + type: Type with: (as-method => true) public defstruct Subfield <: Expression : exp: Expression name: Symbol - type: Type [multi => false] + type: Type with: (as-method => true) public defstruct Index <: Expression : exp: Expression value: Int - type: Type [multi => false] + type: Type with: (as-method => true) public defstruct UIntValue <: Expression : value: Int width: Width @@ -136,19 +136,19 @@ public defstruct DoPrim <: Expression : op: PrimOp args: List<Expression> consts: List<Int> - type: Type [multi => false] + type: Type with: (as-method => true) public defstruct ReadPort <: Expression : mem: Expression index: Expression - type: Type [multi => false] + type: Type with: (as-method => true) enable: Expression public defstruct WritePort <: Expression : mem: Expression index: Expression - type: Type [multi => false] + type: Type with: (as-method => true) enable: Expression public defstruct Register <: Expression : - type: Type [multi => false] + type: Type with: (as-method => true) value: Expression enable: Expression diff --git a/src/main/stanza/firrtl-main.stanza b/src/main/stanza/firrtl-main.stanza index 38b24815..2e9f056a 100644 --- a/src/main/stanza/firrtl-main.stanza +++ b/src/main/stanza/firrtl-main.stanza @@ -1,22 +1,22 @@ -include<"core/stringeater.stanza"> -include<"compiler/lexer.stanza"> -include<"compiler/parser.stanza"> -include<"compiler/rdparser.stanza"> -include<"compiler/macro-utils.stanza"> -include("firrtl-ir.stanza") -include("ir-utils.stanza") -include("ir-parser.stanza") -include("passes.stanza") -include("widthsolver.stanza") +#include<"core/stringeater.stanza"> +#include<"core/macro-utils.stanza"> +#include<"compiler/stz-algorithms.stanza"> +#include<"compiler/stz-lexer.stanza"> +#include<"compiler/stz-parser.stanza"> +#include("firrtl-ir.stanza") +#include("ir-utils.stanza") +#include("ir-parser.stanza") +#include("passes.stanza") +#include("widthsolver.stanza") defpackage firrtl-main : import core import verse - import firrtl.parser - import firrtl.passes - import stanza.lexer - import stanza.parser - import firrtl.ir-utils + import firrtl/parser + import firrtl/passes + import stz/lexer + import stz/parser + import firrtl/ir-utils defn main () : val arg = commandline-arguments() diff --git a/src/main/stanza/firrtl-test-main.stanza b/src/main/stanza/firrtl-test-main.stanza index f7d84600..16351edd 100644 --- a/src/main/stanza/firrtl-test-main.stanza +++ b/src/main/stanza/firrtl-test-main.stanza @@ -1,22 +1,22 @@ -include<"core/stringeater.stanza"> -include<"compiler/lexer.stanza"> -include<"compiler/parser.stanza"> -include<"compiler/rdparser.stanza"> -include<"compiler/macro-utils.stanza"> -include("firrtl-ir.stanza") -include("ir-utils.stanza") -include("ir-parser.stanza") -include("passes.stanza") -include("widthsolver.stanza") +#include<"core/stringeater.stanza"> +#include<"core/macro-utils.stanza"> +#include<"compiler/stz-algorithms.stanza"> +#include<"compiler/stz-lexer.stanza"> +#include<"compiler/stz-parser.stanza"> +#include("firrtl-ir.stanza") +#include("ir-utils.stanza") +#include("ir-parser.stanza") +#include("passes.stanza") +#include("widthsolver.stanza") defpackage firrtl-main : import core import verse - import firrtl.parser - import firrtl.passes - import stanza.lexer - import stanza.parser - import firrtl.ir-utils + import firrtl/parser + import firrtl/passes + import stz/lexer + import stz/parser + import firrtl/ir-utils defn set-printvars! (p:List<Char>) : if contains(p,'t') : PRINT-TYPES = true diff --git a/src/main/stanza/ir-parser.stanza b/src/main/stanza/ir-parser.stanza index 87458185..491fc22c 100644 --- a/src/main/stanza/ir-parser.stanza +++ b/src/main/stanza/ir-parser.stanza @@ -1,9 +1,9 @@ -defpackage firrtl.parser : +defpackage firrtl/parser : import core import verse - import firrtl.ir2 - import stanza.rdparser - import stanza.lexer + import firrtl/ir2 + import stz/parser + import stz/lexer ;======= Convenience Functions ==== defn throw-error (x) : @@ -14,139 +14,84 @@ defn throw-error (x) : defn ut (x) : unwrap-token(x) -;======== String Splitting ======== -defn substring? (s:String, look:String) : - index-of-string(s, look) != false - -defn index-of-string (s:String, look:String) : - for i in 0 through length(s) - length(look) index-when : - for j in 0 to length(look) all? : - s[i + j] == look[j] - -defn split-string (s:String, split:String) -> List<String> : - defn loop (s:String) -> List<String> : - if length(s) == 0 : - List() - else : - match(index-of-string(s, split)) : - (i:Int) : - val rest = loop(substring(s, i + length(split))) - if i == 0 : List(split, rest) - else : List(substring(s, 0, i), split, rest) - (f:False) : list(s) - loop(s) - -;======= Unwrap Prefix Forms ============ -defn unwrap-prefix-form (form) -> ? : - match(form) : - (form:Token) : - val fs = unwrap-prefix-form(item(form)) - List(Token(head(fs), info(form)), tail(fs)) - (form:List) : - if tagged-list?(form, `(@get @do @do-afn @of)) : - val rest = map-append(unwrap-prefix-form, tailn(form, 2)) - val form* = List(form[0], rest) - append(unwrap-prefix-form(form[1]), list(form*)) - else : - list(map-append(unwrap-prefix-form, form)) - (form) : - list(form) - -;======= Split Dots ============ -defn split-dots (forms:List) -> ? : - defn to-form (x:String) : - val num? = for c in x all? : - c >= '0' and c <= '9' - to-int(x) when num? else to-symbol(x) - defn split (form) -> List: - match(ut(form)) : - (f:Symbol) : - val fstr = to-string(f) - if contains?(fstr, '.') : map(to-form, split-string(fstr, ".")) - else : list(form) - (f:List) : - list(map-append(split, f)) - (f) : - list(f) - head(split(forms)) - -;====== Normalize Dots ======== -defn normalize-dots (forms:List) : - val forms* = head(unwrap-prefix-form(forms)) - split-dots(forms*) - ;======== SYNTAX ======================= -rd.defsyntax firrtl : +defsyntax firrtl : + defrule : + symbol = (?x) when ut(x) typeof Symbol : ut(x) + int = (?x) when ut(x) typeof Int : ut(x) + defrule circuit : - (circuit ?name:#symbol : (?module-form ...)) : - rd.match-syntax(normalize-dots(module-form)) : - (?modules:#module ...) : - Circuit(modules, ut(name)) + circuit = (circuit ?name:#symbol : (?modules:#module ... ?rest ...)) : + if not empty?(rest) : + throw-error("Expected module here: ~" << [rest]) + Circuit(modules, name) defrule module : - (module ?name:#symbol : (?ports:#port ... ?body:#comm ...)) : - Module(ut(name), ports, Begin(body)) + module = (module ?name:#symbol : (?ports:#port ... ?body:#comm ... ?rest ...)) : + if not empty?(rest) : + throw-error("Expected command here: ~" << [rest]) + Module(name, ports, Begin(body)) defrule field : - (?name:#symbol : ?type:#type) : + field = (?name:#symbol : ?type:#type) : Field(ut(name), DEFAULT, type) - (flip ?name:#symbol : ?type:#type) : + field = (flip ?name:#symbol : ?type:#type) : Field(ut(name), REVERSE, type) defrule port : - (input ?name:#symbol : ?type:#type) : + port = (input ?name:#symbol : ?type:#type) : Port(ut(name), INPUT, type) - (output ?name:#symbol : ?type:#type) : + port = (output ?name:#symbol : ?type:#type) : Port(ut(name), OUTPUT, type) defrule type : - (?type:#type (@get ?size:#int)) : + type = (?type:#type (@get ?size:#int)) : VectorType(type, ut(size)) - (UInt (@do ?width:#int)) : + type = (UInt (@do ?width:#int)) : UIntType(IntWidth(ut(width))) - (UInt) : + type = (UInt) : UIntType(UnknownWidth()) - (SInt (@do ?width:#int)) : + type = (SInt (@do ?width:#int)) : SIntType(IntWidth(ut(width))) - (SInt) : + type = (SInt) : SIntType(UnknownWidth()) - ({?fields:#field ...}) : + type = ({?fields:#field ...}) : BundleType(fields) defrule comm : - (wire ?name:#symbol : ?type:#type) : + comm = (wire ?name:#symbol : ?type:#type) : DefWire(ut(name), type) - (reg ?name:#symbol : ?type:#type) : + comm = (reg ?name:#symbol : ?type:#type) : DefRegister(ut(name), type) - (mem ?name:#symbol : ?type:#type) : + comm = (mem ?name:#symbol : ?type:#type) : DefMemory(ut(name), type) - (inst ?name:#symbol of ?module:#exp) : + comm = (inst ?name:#symbol of ?module:#exp) : DefInstance(ut(name), module) - (node ?name:#symbol = ?exp:#exp) : + comm = (node ?name:#symbol = ?exp:#exp) : DefNode(ut(name), exp) - (accessor ?name:#symbol = ?source:#exp (@get ?index:#exp)) : + comm = (accessor ?name:#symbol = ?source:#exp (@get ?index:#exp)) : DefAccessor(ut(name), source, index) - ((?body:#comm ...)) : + comm = ((?body:#comm ...)) : Begin(body) - (?x:#exp := ?y:#exp) : + comm = (?x:#exp := ?y:#exp) : Connect(x, y) - (?c:#comm/when) : + comm = (?c:#comm/when) : c defrule comm/when : - (when ?pred:#exp : ?conseq:#comm else : ?alt:#comm) : + comm/when = (when ?pred:#exp : ?conseq:#comm else : ?alt:#comm) : Conditionally(pred, conseq, alt) - (when ?pred:#exp : ?conseq:#comm else ?alt:#comm/when) : + comm/when = (when ?pred:#exp : ?conseq:#comm else ?alt:#comm/when) : Conditionally(pred, conseq, alt) - (when ?pred:#exp : ?conseq:#comm) : + comm/when = (when ?pred:#exp : ?conseq:#comm) : Conditionally(pred, conseq, EmptyStmt()) defrule exp : - (?x:#exp . ?f:#int) : + exp = (?x:#exp . ?f:#int) : Index(x, ut(f), UnknownType()) - (?x:#exp . ?f:#symbol) : + exp = (?x:#exp . ?f:#symbol) : Subfield(x, ut(f), UnknownType()) - (?x:#exp-form) : + exp = (?x:#exp-form) : x val operators = HashTable<Symbol, PrimOp>(symbol-hash) @@ -247,21 +192,21 @@ rd.defsyntax firrtl : operators[`bits] = BITS-SELECT-OP defrule exp-form : - (UInt (@do ?value:#int ?width:#int)) : + exp-form = (UInt (@do ?value:#int ?width:#int)) : UIntValue(ut(value), IntWidth(ut(width))) - (UInt (@do ?value:#int)) : + exp-form = (UInt (@do ?value:#int)) : UIntValue(ut(value), UnknownWidth()) - (SInt (@do ?value:#int ?width:#int)) : + exp-form = (SInt (@do ?value:#int ?width:#int)) : SIntValue(ut(value), IntWidth(ut(width))) - (SInt (@do ?value:#int)) : + exp-form = (SInt (@do ?value:#int)) : SIntValue(ut(value), UnknownWidth()) - (WritePort (@do ?mem:#exp ?index:#exp ?enable:#exp)) : + exp-form = (WritePort (@do ?mem:#exp ?index:#exp ?enable:#exp)) : WritePort(mem, index, UnknownType(), enable) - (ReadPort (@do ?mem:#exp ?index:#exp ?enable:#exp)) : + exp-form = (ReadPort (@do ?mem:#exp ?index:#exp ?enable:#exp)) : ReadPort(mem, index, UnknownType(), enable) - (Register (@do ?value:#exp ?enable:#exp)) : + exp-form = (Register (@do ?value:#exp ?enable:#exp)) : Register(UnknownType(),value,enable) - (?op:#symbol (@do ?es:#exp ... ?ints:#int ...)) : + exp-form = (?op:#symbol (@do ?es:#exp ... ?ints:#int ...)) : println("Op-symbol is:~" % [op]) match(get?(operators, ut(op), false)) : (op:PrimOp) : @@ -270,11 +215,11 @@ rd.defsyntax firrtl : (f:False) : throw-error $ string-join $ [ "Invalid operator: " op] - (?x:#symbol) : + exp-form = (?x:#symbol) : Ref(ut(x), UnknownType()) public defn parse-firrtl (forms:List) : - with-parser{`firrtl, _} $ fn () : - rd.match-syntax(forms) : + with-syntax(firrtl) : + match-syntax(forms) : (?c:#circuit) : c diff --git a/src/main/stanza/ir-utils.stanza b/src/main/stanza/ir-utils.stanza index 1f33547e..80cd39a7 100644 --- a/src/main/stanza/ir-utils.stanza +++ b/src/main/stanza/ir-utils.stanza @@ -1,7 +1,7 @@ -defpackage firrtl.ir-utils : +defpackage firrtl/ir-utils : import core import verse - import firrtl.ir2 + import firrtl/ir2 ;============== DEBUG STUFF ============================= diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza index 313191c8..f5bd655a 100644 --- a/src/main/stanza/passes.stanza +++ b/src/main/stanza/passes.stanza @@ -1,8 +1,8 @@ -defpackage firrtl.passes : +defpackage firrtl/passes : import core import verse - import firrtl.ir2 - import firrtl.ir-utils + import firrtl/ir2 + import firrtl/ir-utils import widthsolver import firrtl-main @@ -36,27 +36,27 @@ public val BI-GENDER = new Gender defstruct WRef <: Expression : name: Symbol - type: Type [multi => false] + type: Type with: (as-method => true) kind: Kind - gender: Gender [multi => false] + gender: Gender with: (as-method => true) defstruct WRegInit <: Expression : reg: Expression name: Symbol - type: Type [multi => false] - gender: Gender [multi => false] + type: Type with: (as-method => true) + gender: Gender with: (as-method => true) defstruct WSubfield <: Expression : exp: Expression name: Symbol - type: Type [multi => false] - gender: Gender [multi => false] + type: Type with: (as-method => true) + gender: Gender with: (as-method => true) defstruct WIndex <: Expression : exp: Expression value: Int - type: Type [multi => false] - gender: Gender [multi => false] + type: Type with: (as-method => true) + gender: Gender with: (as-method => true) defstruct WDefAccessor <: Stmt : name: Symbol @@ -893,10 +893,10 @@ defn lower-module (m:Module,table:HashTable<Symbol,List<KeyValue<Expression,Flip (s:DefWire) : table[name(s)] = get-entries(name(s),type(s)) (s:DefRegister) : val regs = get-entries(name(s),type(s)) - val init-sym = symbol-join([name(s),`.init]) + val init-sym = symbol-join([name(s),`\|.init|]) val init-regs = for r in regs map : val [e f] = [key(r) value(r)] - WRegInit(e,symbol-join([name(e),`.init]),type(e),gender(e)) => f + WRegInit(e,symbol-join([name(e),`\|.init|]),type(e),gender(e)) => f table[name(s)] = regs table[init-sym] = init-regs (s:DefInstance) : diff --git a/src/main/stanza/widthsolver.stanza b/src/main/stanza/widthsolver.stanza index 4c9da2c6..2b967f44 100644 --- a/src/main/stanza/widthsolver.stanza +++ b/src/main/stanza/widthsolver.stanza @@ -1,12 +1,12 @@ ;Define the STANDALONE flag to run STANDALONE -if-defined(STANDALONE) : - include<"core/stringeater.stanza"> - include<"compiler/lexer.stanza"> +#if-defined(STANDALONE) : + #include<"core/stringeater.stanza"> + #include<"compiler/lexer.stanza"> defpackage widthsolver : import core import verse - import stanza.lexer + import stz/lexer ;============= Language of Constraints ====================== public definterface WConstraint @@ -286,7 +286,7 @@ public defn solve-widths (cs: Streamable<WConstraint>) : backsubstitute(keys(eqns), solns) ;================= Main ===================================== -if-defined(STANDALONE) : +#if-defined(STANDALONE) : defn main () : val input = lex(commandline-arguments()) error("No input file!") when length(input) < 2 |
