Explicitly initialize firrtl.stage.Forms to prevent multi-thread collisions (#1463)

* Explicitly initialize firrtl.stage.Forms to prevent multi-thread collisions
See https://github.com/freechipsproject/firrtl/issues/1462.
Convert `lazy val` members of firrtl.stage.Forms to plan `val`s.
Reference firrtl.stage.Forms in sufficient locations to ensure the object is initialized before its members are accessed.

* Respond to comments - make _dummyForms private.

* Move Forms initialization to package object.

* Merge with master

3 files changed, 15 insertions, 13 deletions

diff --git a/src/main/scala/firrtl/options/Stage.scala b/src/main/scala/firrtl/options/Stage.scala
index 3752b846..2b7bb9d6 100644
--- a/src/main/scala/firrtl/options/Stage.scala
+++ b/src/main/scala/firrtl/options/Stage.scala
@@ -62,7 +62,6 @@ abstract class Stage extends Phase {
   * @param stage the stage to run
   */
 class StageMain(val stage: Stage) {
-
   /** The main function that serves as this stage's command line interface.
     * @param args command line arguments
     */
diff --git a/src/main/scala/firrtl/package.scala b/src/main/scala/firrtl/package.scala
index 1e871c46..c0f48bf0 100644
--- a/src/main/scala/firrtl/package.scala
+++ b/src/main/scala/firrtl/package.scala
@@ -3,6 +3,9 @@
 import firrtl.annotations.Annotation
 
 package object firrtl {
+  // Force initialization of the Forms object - https://github.com/freechipsproject/firrtl/issues/1462
+  private val _dummyForms = firrtl.stage.Forms
+
   implicit def seqToAnnoSeq(xs: Seq[Annotation]) = AnnotationSeq(xs)
   implicit def annoSeqToSeq(as: AnnotationSeq): Seq[Annotation] = as.underlying
 
diff --git a/src/main/scala/firrtl/stage/Forms.scala b/src/main/scala/firrtl/stage/Forms.scala
index f3eabd23..3e9803b7 100644
--- a/src/main/scala/firrtl/stage/Forms.scala
+++ b/src/main/scala/firrtl/stage/Forms.scala
@@ -14,17 +14,17 @@ import firrtl.stage.TransformManager.TransformDependency
 
 object Forms {
 
-  lazy val ChirrtlForm: Seq[TransformDependency] = Seq.empty
+  val ChirrtlForm: Seq[TransformDependency] = Seq.empty
 
-  lazy val MinimalHighForm: Seq[TransformDependency] = ChirrtlForm ++
+  val MinimalHighForm: Seq[TransformDependency] = ChirrtlForm ++
     Seq( Dependency(passes.CheckChirrtl),
          Dependency(passes.CInferTypes),
          Dependency(passes.CInferMDir),
          Dependency(passes.RemoveCHIRRTL) )
 
-  lazy val WorkingIR: Seq[TransformDependency] = MinimalHighForm :+ Dependency(passes.ToWorkingIR)
+  val WorkingIR: Seq[TransformDependency] = MinimalHighForm :+ Dependency(passes.ToWorkingIR)
 
-  lazy val Resolved: Seq[TransformDependency] = WorkingIR ++
+  val Resolved: Seq[TransformDependency] = WorkingIR ++
     Seq( Dependency(passes.CheckHighForm),
          Dependency(passes.ResolveKinds),
          Dependency(passes.InferTypes),
@@ -38,15 +38,15 @@ object Forms {
          Dependency(passes.CheckWidths),
          Dependency[firrtl.transforms.InferResets] )
 
-  lazy val Deduped: Seq[TransformDependency] = Resolved :+ Dependency[firrtl.transforms.DedupModules]
+  val Deduped: Seq[TransformDependency] = Resolved :+ Dependency[firrtl.transforms.DedupModules]
 
-  lazy val HighForm: Seq[TransformDependency] = ChirrtlForm ++
+  val HighForm: Seq[TransformDependency] = ChirrtlForm ++
     MinimalHighForm ++
     WorkingIR ++
     Resolved ++
     Deduped
 
-  lazy val MidForm: Seq[TransformDependency] = HighForm ++
+  val MidForm: Seq[TransformDependency] = HighForm ++
     Seq( Dependency(passes.PullMuxes),
          Dependency(passes.ReplaceAccesses),
          Dependency(passes.ExpandConnects),
@@ -56,7 +56,7 @@ object Forms {
          Dependency(passes.ConvertFixedToSInt),
          Dependency(passes.ZeroWidth) )
 
-  lazy val LowForm: Seq[TransformDependency] = MidForm ++
+  val LowForm: Seq[TransformDependency] = MidForm ++
     Seq( Dependency(passes.LowerTypes),
          Dependency(passes.Legalize),
          Dependency(firrtl.transforms.RemoveReset),
@@ -64,19 +64,19 @@ object Forms {
          Dependency[checks.CheckResets],
          Dependency[firrtl.transforms.RemoveWires] )
 
-  lazy val LowFormMinimumOptimized: Seq[TransformDependency] = LowForm ++
+  val LowFormMinimumOptimized: Seq[TransformDependency] = LowForm ++
     Seq( Dependency(passes.RemoveValidIf),
          Dependency(passes.memlib.VerilogMemDelays),
          Dependency(passes.SplitExpressions) )
 
-  lazy val LowFormOptimized: Seq[TransformDependency] = LowFormMinimumOptimized ++
+  val LowFormOptimized: Seq[TransformDependency] = LowFormMinimumOptimized ++
     Seq( Dependency[firrtl.transforms.ConstantPropagation],
          Dependency(passes.PadWidths),
          Dependency[firrtl.transforms.CombineCats],
          Dependency(passes.CommonSubexpressionElimination),
          Dependency[firrtl.transforms.DeadCodeElimination] )
 
-  lazy val VerilogMinimumOptimized: Seq[TransformDependency] = LowFormMinimumOptimized ++
+  val VerilogMinimumOptimized: Seq[TransformDependency] = LowFormMinimumOptimized ++
     Seq( Dependency[firrtl.transforms.BlackBoxSourceHelper],
          Dependency[firrtl.transforms.FixAddingNegativeLiterals],
          Dependency[firrtl.transforms.ReplaceTruncatingArithmetic],
@@ -89,6 +89,6 @@ object Forms {
          Dependency(passes.VerilogPrep),
          Dependency[firrtl.AddDescriptionNodes] )
 
-  lazy val VerilogOptimized: Seq[TransformDependency] = LowFormOptimized ++ VerilogMinimumOptimized
+  val VerilogOptimized: Seq[TransformDependency] = LowFormOptimized ++ VerilogMinimumOptimized
 
 }