Bugfix: GroupComponents (#1082)

* Added test to GroupComponentsSpec demonstrating bug

* Added bugfix to GroupComponents for invalid ports of grouped instances

2 files changed, 42 insertions, 0 deletions

diff --git a/src/main/scala/firrtl/transforms/GroupComponents.scala b/src/main/scala/firrtl/transforms/GroupComponents.scala
index 8c36bb6d..6e149762 100644
--- a/src/main/scala/firrtl/transforms/GroupComponents.scala
+++ b/src/main/scala/firrtl/transforms/GroupComponents.scala
@@ -264,6 +264,11 @@ class GroupComponents extends firrtl.Transform {
           val group = byNode(getWRef(c.loc).name)
           groupStatements(group) += Connect(c.info, c.loc, inGroupFixExps(group, topStmts)(c.expr))
           Block(topStmts)
+        case i: IsInvalid if byNode(getWRef(i.expr).name) != "" =>
+          // Sink is in group
+          val group = byNode(getWRef(i.expr).name)
+          groupStatements(group) += i
+          EmptyStmt
         // TODO Attach if all are in a group?
         case _: IsDeclaration | _: Connect | _: Attach =>
           // Sink is in Top
diff --git a/src/test/scala/firrtlTests/transforms/GroupComponentsSpec.scala b/src/test/scala/firrtlTests/transforms/GroupComponentsSpec.scala
index b4c27875..f731073b 100644
--- a/src/test/scala/firrtlTests/transforms/GroupComponentsSpec.scala
+++ b/src/test/scala/firrtlTests/transforms/GroupComponentsSpec.scala
@@ -331,6 +331,43 @@ class GroupComponentsSpec extends MiddleTransformSpec {
       """.stripMargin
     execute(input, check, groups)
   }
+
+  "Instances with uninitialized ports" should "work properly" in {
+    val input =
+      s"""circuit $top :
+         |  module $top :
+         |    input in: UInt<16>
+         |    output out: UInt<16>
+         |    inst other of Other
+         |    other is invalid
+         |    out <= add(in, other.out)
+         |  module Other:
+         |    input in: UInt<16>
+         |    output out: UInt<16>
+         |    out <= add(asUInt(in), UInt(1))
+      """.stripMargin
+    val groups = Seq(
+      GroupAnnotation(Seq(topComp("other")), "Wrapper", "wrapper")
+    )
+    val check =
+      s"""circuit $top :
+         |  module $top :
+         |    input in: UInt<16>
+         |    output out: UInt<16>
+         |    inst wrapper of Wrapper
+         |    out <= add(in, wrapper.other_out)
+         |  module Wrapper :
+         |    output other_out: UInt<16>
+         |    inst other of Other
+         |    other_out <= other.out
+         |    other.in is invalid
+         |  module Other:
+         |    input in: UInt<16>
+         |    output out: UInt<16>
+         |    out <= add(asUInt(in), UInt(1))
+      """.stripMargin
+    execute(input, check, groups)
+  }
 }
 
 class GroupComponentsIntegrationSpec extends FirrtlFlatSpec {