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authorazidar2015-02-18 17:20:11 -0800
committerazidar2015-02-18 17:20:11 -0800
commit50b5ce57d1b823a03725dd0aa2141f300c244bf1 (patch)
tree6fd005a2e07034ff017dfb6bada6b1eeddad2783 /src
parentafde65773fc7b19dd99e0c65f718a96d0466541b (diff)
Added more testing infrastructre, and Makefile to build firrtl
Diffstat (limited to 'src')
-rw-r--r--src/main/stanza/firrtl-main.stanza47
-rw-r--r--src/main/stanza/passes.stanza36
-rw-r--r--src/test/firrtl/firrtl-test.txt40
3 files changed, 67 insertions, 56 deletions
diff --git a/src/main/stanza/firrtl-main.stanza b/src/main/stanza/firrtl-main.stanza
index 574fb101..17672f3d 100644
--- a/src/main/stanza/firrtl-main.stanza
+++ b/src/main/stanza/firrtl-main.stanza
@@ -17,10 +17,53 @@ defpackage chmain :
import stanza.lexer
import stanza.parser
+defn split (s:String,c:Char) -> List<String> :
+ val empty = ""
+
+ defn next-word (s:String,i:Int) -> String|False :
+ if i == length(s) : false
+ else:
+ if (s[i] == c): substring(s,0,i)
+ else: next-word(s,i + 1)
+
+ val next-str = next-word(s,0)
+ if next-str == false : list()
+ else if next-str == empty : split(substring(s,1,length(s)),c)
+ else :
+ val str = next-str as String
+ List(str,split(substring(s,length(str)+1,length(s)),c))
+
defn main () :
- val lexed = lex-file("../../test/firrtl/firrtl-test.txt")
+ val arg = commandline-arguments()
+ println(arg)
+ val args = split(arg,' ')
+ println(args)
+ println(length(args))
+
+ val lexed = lex-file(args[1])
val c = parse-firrtl(lexed)
println(c)
- ;run-passes(c)
+ run-passes(c)
main()
+
+; [a b c] <- a tuple
+;
+; val rest = List(1,2,3)
+; val b = List(0,rest) --> (0,1,2,3)
+; val c = list(0,rest) --> (0,(1,2,3))
+
+; label<Int> myret :
+; for i in 0 to 10 do :
+; if i == 5:
+; myret(i)
+; 0
+
+; val v = Vector<Int>()
+; add(v,10)
+; add(v,20)
+; add(v,32)
+; for x in v do :
+; println(x)
+
+
diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index d5464d84..03a9583b 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -61,6 +61,18 @@ defmethod print (o:OutputStream, k:Kind) :
(k:InstanceKind) : "inst:"
(k:StructuralMemKind) : "smem:"
+defmethod print (o:OutputStream, e:WRef) :
+ print-all(o,[kind(e) name(e)])
+
+defmethod print (o:OutputStream, e:WField) :
+ print-all(o,[exp(e) "." name(e)])
+
+defmethod print (o:OutputStream, e:WIndex) :
+ print-all(o,[exp(e) "." value(e)])
+
+defmethod print (o:OutputStream, s:WDefAccessor) :
+ print-all(o,[dir(s) " accessor " name(s) " = " source(s) "[" index(s) "]"])
+
defmethod map (f: Expression -> Expression, e: WField) :
WField(f(exp(e)), name(e), type(e), dir(e))
@@ -75,7 +87,10 @@ defmulti dir (e:Expression) -> Direction
defmethod dir (e:Expression) :
OUTPUT
-;ADAM========== Bring to Working IR ========================
+;================= Bring to Working IR ========================
+; Returns a new Circuit with Refs, Fields, Indexes and DefAccessors
+; replaced with IR-internal nodes that contain additional
+; information (kind, direction)
defn to-working-ir (c:Circuit) :
defn to-exp (e:Expression) :
@@ -94,19 +109,12 @@ defn to-working-ir (c:Circuit) :
for m in modules(c) map :
Module(name(m), ports(m), to-stmt(body(m)))
-;ADAM========== Printing ===================================
-
-defn print (o:OutputStream, e:WRef) :
- print-all(o,[name(e)])
-defmethod print (o:OutputStream, e:WField) :
- print-all(o,[exp(e) "." name(e)])
-defmethod print (o:OutputStream, e:WIndex) :
- print-all(o,[exp(e) "." value(e)])
-
-defmethod print (o:OutputStream, s:WDefAccessor) :
- print-all(o,[dir(s) " accessor " name(s) " = " source(s) "[" index(s) "]"])
-
;=============== Resolve Kinds =============================
+; It is useful for the compiler to know information about
+; objects referenced. This information is stored in the kind
+; field in WRef. This pass walks the graph and returns a new
+; Circuit where all WRef kinds are resolved
+
defn resolve-kinds (c:Circuit) :
defn resolve-exp (e:Expression, kinds:HashTable<Symbol,Kind>) :
match(e) :
@@ -1858,7 +1866,7 @@ public defn run-passes (c: Circuit) :
do-stage("Working IR", to-working-ir)
do-stage("Resolve Kinds", resolve-kinds)
- do-stage("Make Explicit Reset", make-explicit-reset)
+ ;do-stage("Make Explicit Reset", make-explicit-reset)
;do-stage("Infer Types", infer-types)
;do-stage("Infer Directions", infer-directions)
;do-stage("Expand Accessors", expand-accessors)
diff --git a/src/test/firrtl/firrtl-test.txt b/src/test/firrtl/firrtl-test.txt
deleted file mode 100644
index 1f3db390..00000000
--- a/src/test/firrtl/firrtl-test.txt
+++ /dev/null
@@ -1,40 +0,0 @@
-circuit top :
- module subtracter :
- input x : UInt
- input y : UInt
- output z : UInt
- z := sub-mod(x, y)
- module gcd :
- input a : UInt(16)
- input b : UInt(16)
- input e : UInt(1)
- output z : UInt(16)
- output v : UInt(1)
- reg x : UInt
- reg y : UInt
- x.init := UInt(0)
- y.init := UInt(42)
- when greater(x, y) :
- inst s of subtracter
- s.x := x
- s.y := y
- x := s.z
- else :
- inst s2 of subtracter
- s2.x := x
- s2.y := y
- y := s2.z
- when e :
- x := a
- y := b
- v := equal(v, UInt(0))
- z := x
- module top :
- input a : UInt(16)
- input b : UInt(16)
- output z : UInt
- inst i of gcd
- i.a := a
- i.b := b
- i.e := UInt(1)
- z := i.z