remove Utils.{AND, OR, NOT, EQV}

hidden const props not desirable

5 files changed, 60 insertions, 53 deletions

diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala
index 378eac6d..b5d212e4 100644
--- a/src/main/scala/firrtl/Emitter.scala
+++ b/src/main/scala/firrtl/Emitter.scala
@@ -62,6 +62,26 @@ case class VRandom(width: BigInt) extends Expression {
 }
 class VerilogEmitter extends Emitter {
   val tab = "  "
+  def AND(e1: WrappedExpression, e2: WrappedExpression): Expression = {
+    if (e1 == e2) e1.e1
+    else if ((e1 == we(zero)) | (e2 == we(zero))) zero
+    else if (e1 == we(one)) e2.e1
+    else if (e2 == we(one)) e1.e1
+    else DoPrim(And, Seq(e1.e1, e2.e1), Nil, UIntType(IntWidth(1)))
+  }
+  def OR(e1: WrappedExpression, e2: WrappedExpression): Expression = {
+    if (e1 == e2) e1.e1
+    else if ((e1 == we(one)) | (e2 == we(one))) one
+    else if (e1 == we(zero)) e2.e1
+    else if (e2 == we(zero)) e1.e1
+    else DoPrim(Or, Seq(e1.e1, e2.e1), Nil, UIntType(IntWidth(1)))
+  }
+  def NOT(e: WrappedExpression): Expression = {
+    if (e == we(one)) zero
+    else if (e == we(zero)) one
+    else DoPrim(Eq, Seq(e.e1, zero), Nil, UIntType(IntWidth(1)))
+  }
+
   def wref(n: String, t: Type) = WRef(n, t, ExpKind(), UNKNOWNGENDER)
   def remove_root(ex: Expression): Expression = ex match {
     case ex: WSubField => ex.exp match {
diff --git a/src/main/scala/firrtl/Utils.scala b/src/main/scala/firrtl/Utils.scala
index 29c37294..572d1ccc 100644
--- a/src/main/scala/firrtl/Utils.scala
+++ b/src/main/scala/firrtl/Utils.scala
@@ -98,28 +98,6 @@ object Utils extends LazyLogging {
      val ix = if (i < 0) ((-1 * i) - 1) else i
      ceil_log2(ix + 1) + 1
   }
-  def EQV (e1:Expression,e2:Expression) : Expression =
-     DoPrim(Eq, Seq(e1, e2), Nil, e1.tpe)
-  // TODO: these should be fixed
-  def AND (e1:WrappedExpression,e2:WrappedExpression) : Expression = {
-     if (e1 == e2) e1.e1
-     else if ((e1 == we(zero)) | (e2 == we(zero))) zero
-     else if (e1 == we(one)) e2.e1
-     else if (e2 == we(one)) e1.e1
-     else DoPrim(And,Seq(e1.e1,e2.e1),Seq(),UIntType(IntWidth(1)))
-  }
-  def OR (e1:WrappedExpression,e2:WrappedExpression) : Expression = {
-     if (e1 == e2) e1.e1
-     else if ((e1 == we(one)) | (e2 == we(one))) one
-     else if (e1 == we(zero)) e2.e1
-     else if (e2 == we(zero)) e1.e1
-     else DoPrim(Or,Seq(e1.e1,e2.e1),Seq(),UIntType(IntWidth(1)))
-  }
-  def NOT (e1:WrappedExpression) : Expression = {
-     if (e1 == we(one)) zero
-     else if (e1 == we(zero)) one
-     else DoPrim(Eq,Seq(e1.e1,zero),Seq(),UIntType(IntWidth(1)))
-  }
 
   def create_mask(dt: Type): Type = dt match {
     case t: VectorType => VectorType(create_mask(t.tpe),t.size)
diff --git a/src/main/scala/firrtl/passes/ExpandWhens.scala b/src/main/scala/firrtl/passes/ExpandWhens.scala
index c9c4b7d1..e02e2bf0 100644
--- a/src/main/scala/firrtl/passes/ExpandWhens.scala
+++ b/src/main/scala/firrtl/passes/ExpandWhens.scala
@@ -34,10 +34,6 @@ import firrtl.Mappers._
 import firrtl.PrimOps._
 import firrtl.WrappedExpression._
 
-// Datastructures
-import scala.collection.mutable
-import scala.collection.mutable.{HashMap, LinkedHashMap, ArrayBuffer}
-
 import annotation.tailrec
 
 /** Expand Whens
@@ -49,6 +45,9 @@ import annotation.tailrec
 */
 object ExpandWhens extends Pass {
   def name = "Expand Whens"
+  type Netlist = collection.mutable.LinkedHashMap[WrappedExpression, Expression]
+  type Simlist = collection.mutable.ArrayBuffer[Statement]
+  type Defaults = Seq[collection.mutable.Map[WrappedExpression, Expression]]
 
   // ========== Expand When Utilz ==========
   private def getFemaleRefs(n: String, t: Type, g: Gender): Seq[Expression] = {
@@ -61,7 +60,7 @@ object ExpandWhens extends Pass {
       }
     }
   }
-  private def expandNetlist(netlist: LinkedHashMap[WrappedExpression, Expression]) =
+  private def expandNetlist(netlist: Netlist) =
     netlist map {
       case (k, WInvalid()) => IsInvalid(NoInfo, k.e1)
       case (k, v) => Connect(NoInfo, k.e1, v)
@@ -69,8 +68,7 @@ object ExpandWhens extends Pass {
   // Searches nested scopes of defaults for lvalue
   // defaults uses mutable Map because we are searching LinkedHashMaps and conversion to immutable is VERY slow
   @tailrec
-  private def getDefault(lvalue: WrappedExpression,
-      defaults: Seq[mutable.Map[WrappedExpression, Expression]]): Option[Expression] = {
+  private def getDefault(lvalue: WrappedExpression, defaults: Defaults): Option[Expression] = {
     defaults match {
       case Nil => None
       case head :: tail => head get lvalue match {
@@ -80,18 +78,22 @@ object ExpandWhens extends Pass {
     }
   }
 
+  private def AND(e1: Expression, e2: Expression) =
+    DoPrim(And, Seq(e1, e2), Nil, UIntType(IntWidth(1)))
+  private def NOT(e: Expression) =
+    DoPrim(Eq, Seq(e, zero), Nil, UIntType(IntWidth(1)))
+
   // ------------ Pass -------------------
   def run(c: Circuit): Circuit = {
-    def expandWhens(m: Module): (LinkedHashMap[WrappedExpression, Expression], ArrayBuffer[Statement], Statement) = {
+    def expandWhens(m: Module): (Netlist, Simlist, Statement) = {
       val namespace = Namespace(m)
-      val simlist = ArrayBuffer[Statement]()
+      val simlist = new Simlist
 
       // defaults ideally would be immutable.Map but conversion from mutable.LinkedHashMap to mutable.Map is VERY slow
-      def expandWhens(
-          netlist: LinkedHashMap[WrappedExpression, Expression],
-          defaults: Seq[mutable.Map[WrappedExpression, Expression]],
-          p: Expression)
-          (s: Statement): Statement = s match {
+      def expandWhens(netlist: Netlist,
+                      defaults: Defaults,
+                      p: Expression)
+                      (s: Statement): Statement = s match {
         case w: DefWire =>
           netlist ++= (getFemaleRefs(w.name, w.tpe, BIGENDER) map (ref => we(ref) -> WVoid()))
           w
@@ -105,8 +107,8 @@ object ExpandWhens extends Pass {
           netlist(c.expr) = WInvalid()
           EmptyStmt
         case s: Conditionally =>
-          val conseqNetlist = LinkedHashMap[WrappedExpression, Expression]()
-          val altNetlist = LinkedHashMap[WrappedExpression, Expression]()
+          val conseqNetlist = new Netlist
+          val altNetlist = new Netlist
           val conseqStmt = expandWhens(conseqNetlist, netlist +: defaults, AND(p, s.pred))(s.conseq)
           val altStmt = expandWhens(altNetlist, netlist +: defaults, AND(p, NOT(s.pred)))(s.alt)
 
@@ -145,7 +147,7 @@ object ExpandWhens extends Pass {
           EmptyStmt
         case s => s map expandWhens(netlist, defaults, p)
       }
-      val netlist = LinkedHashMap[WrappedExpression, Expression]()
+      val netlist = new Netlist
       // Add ports to netlist
       netlist ++= (m.ports flatMap { case Port(_, name, dir, tpe) =>
         getFemaleRefs(name, tpe, to_gender(dir)) map (ref => we(ref) -> WVoid())
diff --git a/src/main/scala/firrtl/passes/RemoveAccesses.scala b/src/main/scala/firrtl/passes/RemoveAccesses.scala
index 880d6b1c..08f08eac 100644
--- a/src/main/scala/firrtl/passes/RemoveAccesses.scala
+++ b/src/main/scala/firrtl/passes/RemoveAccesses.scala
@@ -1,11 +1,11 @@
 package firrtl.passes
 
+import firrtl.{WRef, WSubAccess, WSubIndex, WSubField, Namespace}
+import firrtl.PrimOps.{And, Eq}
 import firrtl.ir._
-import firrtl.{WRef, WSubAccess, WSubIndex, WSubField}
 import firrtl.Mappers._
 import firrtl.Utils._
 import firrtl.WrappedExpression._
-import firrtl.Namespace
 import scala.collection.mutable
 
 
@@ -13,6 +13,13 @@ import scala.collection.mutable
   */
 object RemoveAccesses extends Pass {
   def name = "Remove Accesses"
+
+  private def AND(e1: Expression, e2: Expression) =
+    DoPrim(And, Seq(e1, e2), Nil, UIntType(IntWidth(1)))
+
+  private def EQV(e1: Expression, e2: Expression): Expression =
+    DoPrim(Eq, Seq(e1, e2), Nil, e1.tpe)
+
   /** Container for a base expression and its corresponding guard
     */
   private case class Location(base: Expression, guard: Expression)
@@ -53,13 +60,13 @@ object RemoveAccesses extends Pass {
   /** Returns true if e contains a [[firrtl.WSubAccess]]
     */
   private def hasAccess(e: Expression): Boolean = {
-     var ret: Boolean = false
-     def rec_has_access(e: Expression): Expression = {
-       e match {
-         case e : WSubAccess => ret = true
-         case e =>
-       }
-       e map rec_has_access
+    var ret: Boolean = false
+    def rec_has_access(e: Expression): Expression = {
+      e match {
+        case e : WSubAccess => ret = true
+        case e =>
+      }
+      e map rec_has_access
     }
     rec_has_access(e)
     ret
@@ -150,10 +157,9 @@ object RemoveAccesses extends Pass {
       Module(m.info, m.name, m.ports, squashEmpty(onStmt(m.body)))
     }
   
-    val newModules = c.modules.map {
+    c copy (modules = (c.modules map {
       case m: ExtModule => m
       case m: Module => remove_m(m)
-    }
-    Circuit(c.info, newModules, c.main)
+    }))
   }
 }
diff --git a/src/test/scala/firrtlTests/UnitTests.scala b/src/test/scala/firrtlTests/UnitTests.scala
index 2d1bbdc1..7feb4a00 100644
--- a/src/test/scala/firrtlTests/UnitTests.scala
+++ b/src/test/scala/firrtlTests/UnitTests.scala
@@ -203,7 +203,8 @@ class UnitTests extends FirrtlFlatSpec {
       InferWidths,
       PullMuxes,
       ExpandConnects,
-      RemoveAccesses
+      RemoveAccesses,
+      ConstProp
     )
     val input =
       """circuit AssignViaDeref : 
@@ -221,7 +222,7 @@ class UnitTests extends FirrtlFlatSpec {
      val check = Seq(
        """wire GEN_0 : { a : UInt<8>}""",
        """GEN_0.a <= table[0].a""",
-       """when eq(UInt<1>("h1"), UInt<1>("h1")) :""",
+       """when UInt<1>("h1") :""",
        """GEN_0.a <= table[1].a""",
        """wire GEN_1 : UInt<8>""",
        """when eq(UInt<1>("h0"), GEN_0.a) :""",