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authorJack Koenig2019-03-28 18:04:45 -0700
committerGitHub2019-03-28 18:04:45 -0700
commit43768b5a9fcf0f9808a62401b2d4fdfbad7597c2 (patch)
tree204105111d1f2c1b41dabdea0618477d631e4a86 /src
parent24f81e828b70e2745c2fbd06a4694a9f054851e8 (diff)
parent97e132e24226e69afc3a52d88c4a591b0678f816 (diff)
Merge branch 'master' into dce-printf-stop
Diffstat (limited to 'src')
-rw-r--r--src/main/scala/firrtl/passes/RemoveAccesses.scala13
1 files changed, 12 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/passes/RemoveAccesses.scala b/src/main/scala/firrtl/passes/RemoveAccesses.scala
index 961f5aba..2cad4c36 100644
--- a/src/main/scala/firrtl/passes/RemoveAccesses.scala
+++ b/src/main/scala/firrtl/passes/RemoveAccesses.scala
@@ -13,7 +13,7 @@ import scala.collection.mutable
/** Removes all [[firrtl.WSubAccess]] from circuit
*/
-object RemoveAccesses extends Pass {
+class RemoveAccesses extends Pass {
private def AND(e1: Expression, e2: Expression) =
if(e1 == one) e2
else if(e2 == one) e1
@@ -166,3 +166,14 @@ object RemoveAccesses extends Pass {
})
}
}
+
+object RemoveAccesses extends Pass {
+ def apply: Pass = {
+ new RemoveAccesses()
+ }
+
+ def run(c: Circuit): Circuit = {
+ val t = new RemoveAccesses
+ t.run(c)
+ }
+}