fix more bugs in flo backend

1 files changed, 29 insertions, 19 deletions

diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index e6206b60..9a259d27 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -1759,7 +1759,7 @@ defn split-exp (c:Circuit) :
          (e:Subfield|DoPrim|Pad|ReadPort|Register|WritePort) : 
             val n* = 
                if n typeof False : gensym(`T)
-               else : to-symbol $ string-join $ [n as Symbol gensym(`#)]
+               else : to-symbol $ string-join $ [n as Symbol gensym(`#)] 
             add(v,DefNode(n*,e))
             WRef(n*,type(e),NodeKind(),UNKNOWN-GENDER)
          (e) : e
@@ -1901,8 +1901,17 @@ defn emit-all (es:Streamable, top:Symbol) :
        (ex) :            print(ex)
 
 defn emit! (e:Expression,top:Symbol) :
+   defn greater-op? (op: PrimOp) -> True|False :
+      contains?([GREATER-OP, GREATER-UU-OP, GREATER-US-OP, GREATER-SU-OP, GREATER-SS-OP], op)
+   defn greater-eq-op? (op: PrimOp) -> True|False :
+      contains?([GREATER-EQ-OP, GREATER-EQ-UU-OP, GREATER-EQ-US-OP, GREATER-EQ-SU-OP, GREATER-EQ-SS-OP], op)     
+   defn less-eq-op? (op: PrimOp) -> True|False :
+      contains?([LESS-EQ-OP, LESS-EQ-UU-OP, LESS-EQ-US-OP, LESS-EQ-SS-OP, LESS-EQ-SS-OP], op)
+   defn less-op? (op: PrimOp) -> True|False :
+      contains?([LESS-OP, LESS-UU-OP, LESS-US-OP, LESS-SS-OP, LESS-SS-OP], op)
    defn cmp-op? (op: PrimOp) -> True|False :
-      contains?([EQUAL-OP, NEQUAL-OP, GREATER-OP, LESS-EQ-OP, LESS-OP, GREATER-EQ-OP], op)
+      greater-op?(op) or greater-eq-op?(op) or less-op?(op) or less-eq-op?(op) or 
+      contains?([EQUAL-OP, EQUAL-UU-OP, EQUAL-SS-OP, NEQUAL-OP, NEQUAL-UU-OP, NEQUAL-SS-OP], op)
    match(e) :
       (e:Ref) :       emit-all([top "::" name(e)], top)
       (e:UIntValue) : emit-all([value(e) "'" sane-width(width(e))], top)
@@ -1910,7 +1919,7 @@ defn emit! (e:Expression,top:Symbol) :
       (e:Subfield) :  emit-all([exp(e) "/" name(e)], top)
       (e:Index) :     emit-all([exp(e) "/" value(e)], top)
       (e:Pad) : 
-         emit-all(["rsh'" prim-width(type(e)) "  " value(e) "  " width(e)], top)
+         emit-all(["rsh'" prim-width(type(e)) " " value(e) " " width(e)], top)
       (e:Register) : 
          emit-all(["reg'" prim-width(type(e)) " 1 " value(e)], top) ;; enable(e)
       (e:ReadPort) : 
@@ -1918,10 +1927,10 @@ defn emit! (e:Expression,top:Symbol) :
       (e:DoPrim) : 
          if cmp-op?(op(e)) :
            emit-all([flo-op-name(op(e)) "'" prim-width(type(args(e)[0]))], top)
-           if op(e) == GREATER-OP or op(e) == LESS-EQ-OP :
-             emit-all(["  " args(e)[1] " " args(e)[0]], top)
+           if greater-op?(op(e)) or less-eq-op?(op(e)) :
+             emit-all([" " args(e)[1] " " args(e)[0]], top)
            else :
-             emit-all(["  " args(e)[0] " " args(e)[1]], top)
+             emit-all([" " args(e)[0] " " args(e)[1]], top)
          else if op(e) == BIT-SELECT-OP :
            emit-all([flo-op-name(op(e)) "'1 " args(e)[0] " " consts(e)[0]], top)
          else if op(e) == BITS-SELECT-OP :
@@ -1941,7 +1950,7 @@ defn emit! (e:Expression,top:Symbol) :
              for const in consts(e) do :
                print(" ")
                print(const)
-      (e) : print-all(["EMIT(" e ")"])
+      (e) : error("SHOULDN'T EMIT THIS") ;; print-all(["EMIT(" e ")"])
       ;(e) : emit-all(["mov'" prim-width(type(e)) " " e], top) ;TODO, not sure which one is right
 
 defn maybe-mov (e:Expression) -> String :
@@ -1959,21 +1968,22 @@ defn emit-s (s:Stmt, v:List<Symbol>, top:Symbol) :
       (s:DefWire) : ""
       (s:DefInstance) : error("Shouldn't be here")
       (s:DefMemory) :
-           val vtype = type(s) as VectorType
-           emit-all([top "::" name(s) " = mem'" prim-width(type(vtype)) " " size(vtype) "\n"], top)
-      (s:DefNode) : emit-all([top "::" name(s) " = " maybe-mov(value(s)) value(s) "\n"], top)
+         val vtype = type(s) as VectorType
+         emit-all([top "::" name(s) " = mem'" prim-width(type(vtype)) " " size(vtype) "\n"], top)
+      (s:DefNode) :
+         if value(s) typeof WritePort :
+            val e = value(s) as WritePort
+            val n = gensym(`F)
+            emit-all([top "::" n " = wr'" prim-width(type(e)) " " enable(e) " " mem(e) " " index(e) " " name(s) "\n"], top)
+         else :
+           emit-all([top "::" name(s) " = " maybe-mov(value(s)) value(s) "\n"], top)
       (s:Begin) : do(emit-s{_, v, top}, body(s))
       (s:Connect) : 
-         if loc(s) typeof WritePort :
-            val e = loc(s) as WritePort
-            val name = gensym(`F)
-            emit-all([top "::" name " = wr'" prim-width(type(e)) " " enable(e) " " top "::" mem(e) " " index(e) " " exp(s) "\n"], top)
+         val n = name(loc(s) as Ref)
+         if contains?(v,n) :
+            emit-all([top "::" n " = out'" prim-width(type(loc(s))) " " exp(s) "\n"], top)
          else :
-            val n = name(loc(s) as Ref)
-            if contains?(v,n) :
-               emit-all([top "::" n " = out'" prim-width(type(loc(s))) " " exp(s) "\n"], top)
-            else :
-               emit-all([top "::" n " = " maybe-mov(exp(s)) exp(s) "\n"], top)
+            emit-all([top "::" n " = " maybe-mov(exp(s)) exp(s) "\n"], top)
       (s) : s 
 
 defn emit-module (m:Module) :