Remove FlagUtils and related unused debug printing

5 files changed, 36 insertions, 64 deletions

diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala
index 94eca465..afa414c5 100644
--- a/src/main/scala/firrtl/Emitter.scala
+++ b/src/main/scala/firrtl/Emitter.scala
@@ -98,10 +98,10 @@ object VerilogEmitter extends Emitter {
                case (e:DoPrim) => emit2(op_stream(e), top + 1)
                case (e:Mux) => emit2(Seq(e.cond," ? ",cast(e.tval)," : ",cast(e.fval)),top + 1)
                case (e:ValidIf) => emit2(Seq(cast(e.value)),top + 1)
-               case (e:WRef) => w.get.write(e.serialize())
+               case (e:WRef) => w.get.write(e.serialize)
                case (e:WSubField) => w.get.write(lowered_name(e))
                case (e:WSubAccess) => w.get.write(lowered_name(e.exp) + "[" + lowered_name(e.index) + "]")
-               case (e:WSubIndex) => w.get.write(e.serialize())
+               case (e:WSubIndex) => w.get.write(e.serialize)
                case (_:UIntValue|_:SIntValue) => v_print(e)
             }
          }
@@ -114,7 +114,7 @@ object VerilogEmitter extends Emitter {
                case (t:VectorType) => 
                   emit2(t.tpe, top + 1)
                   w.get.write("[" + (t.size - 1) + ":0]")
-               case (t) => error("Shouldn't be here"); w.get.write(t.serialize())
+               case (t) => error("Shouldn't be here"); w.get.write(t.serialize)
             }
          }
          case (p:Direction) => {
diff --git a/src/main/scala/firrtl/Utils.scala b/src/main/scala/firrtl/Utils.scala
index 5fad46bc..7944126b 100644
--- a/src/main/scala/firrtl/Utils.scala
+++ b/src/main/scala/firrtl/Utils.scala
@@ -47,10 +47,6 @@ import scala.collection.mutable.LinkedHashMap
 //import scala.reflect.runtime.universe._
 
 object Utils {
-//
-//   // Is there a more elegant way to do this?
-   private type FlagMap = Map[String, Boolean]
-   private val FlagMap = Map[String, Boolean]().withDefaultValue(false)
    implicit class WithAs[T](x: T) {
      import scala.reflect._
      def as[O: ClassTag]: Option[O] = x match {
@@ -298,24 +294,9 @@ object Utils {
    }
 // =================================
    def error(str:String) = throw new FIRRTLException(str)
-   def debug(node: AST)(implicit flags: FlagMap): String = {
-     if (!flags.isEmpty) {
-       var str = ""
-       if (flags("types")) {
-         val tpe = node.getType
-         tpe match {
-            case t:UnknownType => str += s"@<t:${tpe.wipeWidth.serialize}>"
-         }
-       }
-       str
-     }
-     else {
-       ""
-     }
-   }
 
    implicit class BigIntUtils(bi: BigInt){
-     def serialize(implicit flags: FlagMap = FlagMap): String = 
+     def serialize: String =
         if (bi < BigInt(0)) "\"h" + bi.toString(16).substring(1) + "\""
         else "\"h" + bi.toString(16) + "\""
    }
@@ -333,7 +314,7 @@ object Utils {
    }
 
    implicit class PrimOpUtils(op: PrimOp) {
-     def serialize(implicit flags: FlagMap = FlagMap): String = op.getString
+     def serialize: String = op.getString
    }
 
 //// =============== EXPANSION FUNCTIONS ================
@@ -808,8 +789,8 @@ object Utils {
    //  }
    //}
    implicit class ExpUtils(exp: Expression) {
-     def serialize(implicit flags: FlagMap = FlagMap): String = {
-       val ret = exp match {
+     def serialize: String = {
+       exp match {
          case v: UIntValue => s"UInt${v.width.serialize}(${v.value.serialize})"
          case v: SIntValue => s"SInt${v.width.serialize}(${v.value.serialize})"
          case r: Ref => r.name
@@ -826,7 +807,6 @@ object Utils {
          case s: WSubAccess => s"${s.exp.serialize}[${s.index.serialize}]"
          case r: WVoid => "VOID"
        } 
-       ret + debug(exp)
      }
    }
 
@@ -846,16 +826,16 @@ object Utils {
    //}
 
    implicit class StmtUtils(stmt: Stmt) {
-     def serialize(implicit flags: FlagMap = FlagMap): String =
+     def serialize: String =
      {
-       var ret = stmt match {
+       stmt match {
          case w: DefWire => s"wire ${w.name} : ${w.tpe.serialize}"
          case r: DefRegister => 
            val str = new StringBuilder(s"reg ${r.name} : ${r.tpe.serialize}, ${r.clock.serialize} with : ")
            withIndent {
              str ++= newline + s"reset => (${r.reset.serialize}, ${r.init.serialize})"
            }
-           str
+           str.toString
          case i: DefInstance => s"inst ${i.name} of ${i.module}"
          case i: WDefInstance => s"inst ${i.name} of ${i.module}"
          case m: DefMemory => {
@@ -897,7 +877,7 @@ object Utils {
                if (i != 0) s ++= newline ++ b.stmts(i).serialize
                else s ++= b.stmts(i).serialize
             }
-            s.result + debug(b)
+            s.result
          } 
          case i: IsInvalid => s"${i.exp.serialize} is invalid"
          case s: Stop => s"stop(${s.clk.serialize}, ${s.en.serialize}, ${s.ret})"
@@ -921,7 +901,6 @@ object Utils {
             s"${dir} mport ${s.name} = ${s.mem}[${s.exps(0)}], s.exps(1)"
          }
        } 
-       ret + debug(stmt)
      }
 
      // Using implicit types to allow overloading of function type to map, see StmtMagnet above
@@ -954,23 +933,21 @@ object Utils {
    }
 
    implicit class WidthUtils(w: Width) {
-     def serialize(implicit flags: FlagMap = FlagMap): String = {
-       val s = w match {
+     def serialize: String = {
+       w match {
          case w:UnknownWidth => "" //"?"
          case w: IntWidth => s"<${w.width.toString}>"
          case w: VarWidth => s"<${w.name}>"
        } 
-       s + debug(w)
      }
    }
 
    implicit class FlipUtils(f: Flip) {
-     def serialize(implicit flags: FlagMap = FlagMap): String = {
-       val s = f match {
+     def serialize: String = {
+       f match {
          case REVERSE => "flip "
          case DEFAULT => ""
        } 
-       s + debug(f)
      }
      def flip(): Flip = {
        f match {
@@ -988,8 +965,8 @@ object Utils {
    }
 
    implicit class FieldUtils(field: Field) {
-     def serialize(implicit flags: FlagMap = FlagMap): String = 
-       s"${field.flip.serialize}${field.name} : ${field.tpe.serialize}" + debug(field)
+     def serialize: String =
+       s"${field.flip.serialize}${field.name} : ${field.tpe.serialize}"
      def flip(): Field = Field(field.name, field.flip.flip, field.tpe)
 
      def getType(): Type = field.tpe
@@ -997,9 +974,9 @@ object Utils {
    }
 
    implicit class TypeUtils(t: Type) {
-     def serialize(implicit flags: FlagMap = FlagMap): String = {
+     def serialize: String = {
        val commas = ", " // for mkString in BundleType
-         val s = t match {
+         t match {
            case c:ClockType => "Clock"
            //case UnknownType => "UnknownType"
            case u:UnknownType => "?"
@@ -1008,7 +985,6 @@ object Utils {
            case t: BundleType => s"{ ${t.fields.map(_.serialize).mkString(commas)}}"
            case t: VectorType => s"${t.tpe.serialize}[${t.size}]"
          } 
-         s + debug(t)
      }
 
      def getType(): Type = 
@@ -1026,12 +1002,11 @@ object Utils {
    }
 
    implicit class DirectionUtils(d: Direction) {
-     def serialize(implicit flags: FlagMap = FlagMap): String = {
-       val s = d match {
+     def serialize: String = {
+       d match {
          case INPUT => "input"
          case OUTPUT => "output"
        } 
-       s + debug(d)
      }
      def toFlip(): Flip = {
        d match {
@@ -1042,14 +1017,14 @@ object Utils {
    }
 
    implicit class PortUtils(p: Port) {
-     def serialize(implicit flags: FlagMap = FlagMap): String = 
-       s"${p.direction.serialize} ${p.name} : ${p.tpe.serialize}" + debug(p)
+     def serialize: String =
+       s"${p.direction.serialize} ${p.name} : ${p.tpe.serialize}"
      def getType(): Type = p.tpe
      def toField(): Field = Field(p.name, p.direction.toFlip, p.tpe)
    }
 
    implicit class ModuleUtils(m: Module) {
-     def serialize(implicit flags: FlagMap = FlagMap): String = {
+     def serialize: String = {
        m match {
           case m:InModule => {
              var s = new StringBuilder(s"module ${m.name} : ")
@@ -1057,7 +1032,6 @@ object Utils {
                s ++= m.ports.map(newline ++ _.serialize).mkString
                s ++= newline ++ m.body.serialize
              }
-             s ++= debug(m)
              s.toString
           }
           case m:ExModule => {
@@ -1066,7 +1040,6 @@ object Utils {
                s ++= m.ports.map(newline ++ _.serialize).mkString
                s ++= newline
              }
-             s ++= debug(m)
              s.toString
           }
        }
@@ -1074,11 +1047,10 @@ object Utils {
    }
 
    implicit class CircuitUtils(c: Circuit) {
-     def serialize(implicit flags: FlagMap = FlagMap): String = {
+     def serialize: String = {
        var s = new StringBuilder(s"circuit ${c.main} : ")
        withIndent { s ++= newline ++ c.modules.map(_.serialize).mkString(newline + newline) }
        s ++= newline ++ newline
-       s ++= debug(c)
        s.toString
      }
    }
diff --git a/src/main/scala/firrtl/WIR.scala b/src/main/scala/firrtl/WIR.scala
index 9c7b85ee..9b10129b 100644
--- a/src/main/scala/firrtl/WIR.scala
+++ b/src/main/scala/firrtl/WIR.scala
@@ -91,8 +91,8 @@ class WrappedExpression (val e1:Expression) {
          case _ => false
       }
    }
-   override def hashCode = e1.serialize().hashCode
-   override def toString = e1.serialize()
+   override def hashCode = e1.serialize.hashCode
+   override def toString = e1.serialize
 }
       
 
diff --git a/src/main/scala/firrtl/passes/Checks.scala b/src/main/scala/firrtl/passes/Checks.scala
index 0a07fdcb..71b00aaf 100644
--- a/src/main/scala/firrtl/passes/Checks.scala
+++ b/src/main/scala/firrtl/passes/Checks.scala
@@ -331,26 +331,26 @@ object CheckTypes extends Pass with LazyLogging {
          for (x <- ls) {
             if (wt(tpe(ls.head)) != wt(tpe(x))) error = true
          }
-         if (error) errors += new OpNotAllSameType(info,e.op.serialize()) 
+         if (error) errors += new OpNotAllSameType(info,e.op.serialize)
       }
       def all_ground (ls:Seq[Expression]) : Unit = {
          var error = false
          for (x <- ls ) {
             if (!(tpe(x).typeof[UIntType] || tpe(x).typeof[SIntType])) error = true
          }
-         if (error) errors += new OpNotGround(info,e.op.serialize()) 
+         if (error) errors += new OpNotGround(info,e.op.serialize)
       }
       def all_uint (ls:Seq[Expression]) : Unit = {
          var error = false
          for (x <- ls ) {
             if (!(tpe(x).typeof[UIntType])) error = true
          }
-         if (error) errors += new OpNotAllUInt(info,e.op.serialize()) 
+         if (error) errors += new OpNotAllUInt(info,e.op.serialize)
       }
       def is_uint (x:Expression) : Unit = {
          var error = false
          if (!(tpe(x).typeof[UIntType])) error = true
-         if (error) errors += new OpNotUInt(info,e.op.serialize(),x.serialize()) 
+         if (error) errors += new OpNotUInt(info,e.op.serialize,x.serialize)
       }
       
       e.op match {
@@ -571,14 +571,14 @@ object CheckGenders extends Pass {
          //println(desired == gender)
          //if gender != desired and gender != BI-GENDER:
          (gender,desired) match {
-            case (MALE, FEMALE) => errors += new WrongGender(info,e.serialize(),as_srcsnk(desired),as_srcsnk(gender))
+            case (MALE, FEMALE) => errors += new WrongGender(info,e.serialize,as_srcsnk(desired),as_srcsnk(gender))
             case (FEMALE, MALE) =>
                if ((kindx == PortKind() || kindx == InstanceKind()) && has_flipQ == false) {
                   //; OK!
                   false
                } else {
                   //; Not Ok!
-                  errors += new WrongGender(info,e.serialize(),as_srcsnk(desired),as_srcsnk(gender))
+                  errors += new WrongGender(info,e.serialize,as_srcsnk(desired),as_srcsnk(gender))
                }
             case _ => false
          }
@@ -696,7 +696,7 @@ object CheckWidths extends Pass with StanzaPass {
                   (e.width) match { 
                      case (w:IntWidth) => 
                         if (scala.math.max(1,e.value.bitLength) > w.width) {
-                           errors += new WidthTooSmall(info,e.value.serialize())
+                           errors += new WidthTooSmall(info,e.value.serialize)
                         }
                      case (w) => errors += new UninferredWidth(info)
                   }
@@ -705,7 +705,7 @@ object CheckWidths extends Pass with StanzaPass {
                case (e:SIntValue) => {
                   (e.width) match { 
                      case (w:IntWidth) => 
-                        if (e.value.bitLength + 1 > w.width) errors += new WidthTooSmall(info,e.value.serialize())
+                        if (e.value.bitLength + 1 > w.width) errors += new WidthTooSmall(info,e.value.serialize)
                      case (w) => errors += new UninferredWidth(info)
                   }
                   check_width_w(info)(e.width)
diff --git a/src/main/scala/firrtl/passes/Passes.scala b/src/main/scala/firrtl/passes/Passes.scala
index 69372b9f..49637d12 100644
--- a/src/main/scala/firrtl/passes/Passes.scala
+++ b/src/main/scala/firrtl/passes/Passes.scala
@@ -85,7 +85,7 @@ object PassUtils extends LazyLogging {
        val name = p.name
        logger.debug(s"Starting ${name}")
        val x = p.run(c)
-       logger.debug(x.serialize())
+       logger.debug(x.serialize)
        logger.debug(s"Finished ${name}")
        executePasses(x, passes.tail)
     }