diff options
| author | azidar | 2015-03-03 17:26:40 -0800 |
|---|---|---|
| committer | azidar | 2015-03-03 17:26:40 -0800 |
| commit | 355749c83d2066f1a149333ed762a7945d405076 (patch) | |
| tree | 77c47b9d3ef3eb91cfb0d56ad376a3c7a94536db /src | |
| parent | 36b2fa287c3931ff7eec0b18c23070cdd9f21c15 (diff) | |
In progress for type inference. Looks like other code is breaking, and i dont understand why
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/stanza/firrtl-ir.stanza | 37 | ||||
| -rw-r--r-- | src/main/stanza/ir-parser.stanza | 90 | ||||
| -rw-r--r-- | src/main/stanza/ir-utils.stanza | 101 | ||||
| -rw-r--r-- | src/main/stanza/passes.stanza | 260 |
4 files changed, 335 insertions, 153 deletions
diff --git a/src/main/stanza/firrtl-ir.stanza b/src/main/stanza/firrtl-ir.stanza index 206401d8..dc06e891 100644 --- a/src/main/stanza/firrtl-ir.stanza +++ b/src/main/stanza/firrtl-ir.stanza @@ -23,21 +23,31 @@ public val SUB-UU-OP = PrimOp() public val SUB-US-OP = PrimOp() public val SUB-SU-OP = PrimOp() public val SUB-SS-OP = PrimOp() -public val TIMES-OP = PrimOp() -public val TIMES-UU-OP = PrimOp() -public val TIMES-US-OP = PrimOp() -public val TIMES-SU-OP = PrimOp() -public val TIMES-SS-OP = PrimOp() -public val DIVIDE-OP = PrimOp() -public val DIVIDE-UU-OP = PrimOp() -public val DIVIDE-US-OP = PrimOp() -public val DIVIDE-SU-OP = PrimOp() -public val DIVIDE-SS-OP = PrimOp() +public val MUL-OP = PrimOp() +public val MUL-UU-OP = PrimOp() +public val MUL-US-OP = PrimOp() +public val MUL-SU-OP = PrimOp() +public val MUL-SS-OP = PrimOp() +public val DIV-OP = PrimOp() +public val DIV-UU-OP = PrimOp() +public val DIV-US-OP = PrimOp() +public val DIV-SU-OP = PrimOp() +public val DIV-SS-OP = PrimOp() public val MOD-OP = PrimOp() public val MOD-UU-OP = PrimOp() public val MOD-US-OP = PrimOp() public val MOD-SU-OP = PrimOp() public val MOD-SS-OP = PrimOp() +public val QUO-OP = PrimOp() +public val QUO-UU-OP = PrimOp() +public val QUO-US-OP = PrimOp() +public val QUO-SU-OP = PrimOp() +public val QUO-SS-OP = PrimOp() +public val REM-OP = PrimOp() +public val REM-UU-OP = PrimOp() +public val REM-US-OP = PrimOp() +public val REM-SU-OP = PrimOp() +public val REM-SS-OP = PrimOp() public val ADD-WRAP-OP = PrimOp() public val ADD-WRAP-UU-OP = PrimOp() public val ADD-WRAP-US-OP = PrimOp() @@ -71,9 +81,9 @@ public val GREATER-EQ-SS-OP = PrimOp() public val EQUAL-OP = PrimOp() public val EQUAL-UU-OP = PrimOp() public val EQUAL-SS-OP = PrimOp() -public val MULTIPLEX-OP = PrimOp() -public val MULTIPLEX-UU-OP = PrimOp() -public val MULTIPLEX-SS-OP = PrimOp() +public val MUX-OP = PrimOp() +public val MUX-UU-OP = PrimOp() +public val MUX-SS-OP = PrimOp() public val PAD-OP = PrimOp() public val PAD-U-OP = PrimOp() public val PAD-S-OP = PrimOp() @@ -86,6 +96,7 @@ public val AS-SINT-S-OP = PrimOp() public val SHIFT-LEFT-OP = PrimOp() public val SHIFT-LEFT-U-OP = PrimOp() public val SHIFT-LEFT-S-OP = PrimOp() +public val SHIFT-RIGHT-OP = PrimOp() public val SHIFT-RIGHT-U-OP = PrimOp() public val SHIFT-RIGHT-S-OP = PrimOp() public val CONVERT-OP = PrimOp() diff --git a/src/main/stanza/ir-parser.stanza b/src/main/stanza/ir-parser.stanza index 34dbcec7..43383f9a 100644 --- a/src/main/stanza/ir-parser.stanza +++ b/src/main/stanza/ir-parser.stanza @@ -157,24 +157,98 @@ rd.defsyntax firrtl : val operators = HashTable<Symbol, PrimOp>(symbol-hash) operators[`add] = ADD-OP - operators[`add-mod] = ADD-MOD-OP + operators[`add-uu] = ADD-UU-OP + operators[`add-us] = ADD-US-OP + operators[`add-su] = ADD-SU-OP + operators[`add-ss] = ADD-SS-OP operators[`sub] = SUB-OP - operators[`sub-mod] = SUB-MOD-OP - operators[`times] = TIMES-OP + operators[`sub-uu] = SUB-UU-OP + operators[`sub-us] = SUB-US-OP + operators[`sub-su] = SUB-SU-OP + operators[`sub-ss] = SUB-SS-OP + operators[`mul] = MUL-OP + operators[`mul-uu] = MUL-UU-OP + operators[`mul-us] = MUL-US-OP + operators[`mul-su] = MUL-SU-OP + operators[`mul-ss] = MUL-SS-OP + operators[`div] = DIV-OP + operators[`div-uu] = DIV-UU-OP + operators[`div-us] = DIV-US-OP + operators[`div-su] = DIV-SU-OP + operators[`div-ss] = DIV-SS-OP operators[`mod] = MOD-OP - operators[`bit-and] = BIT-AND-OP - operators[`bit-or] = BIT-OR-OP - operators[`bit-xor] = BIT-XOR-OP - operators[`concat] = CONCAT-OP + operators[`mod-uu] = MOD-UU-OP + operators[`mod-us] = MOD-US-OP + operators[`mod-su] = MOD-SU-OP + operators[`mod-ss] = MOD-SS-OP + operators[`quo] = QUO-OP + operators[`quo-uu] = QUO-UU-OP + operators[`quo-us] = QUO-US-OP + operators[`quo-su] = QUO-SU-OP + operators[`quo-ss] = QUO-SS-OP + operators[`rem] = REM-OP + operators[`rem-uu] = REM-UU-OP + operators[`rem-us] = REM-US-OP + operators[`rem-su] = REM-SU-OP + operators[`rem-ss] = REM-SS-OP + operators[`add-wrap] = ADD-WRAP-OP + operators[`add-wrap-uu] = ADD-WRAP-UU-OP + operators[`add-wrap-us] = ADD-WRAP-US-OP + operators[`add-wrap-su] = ADD-WRAP-SU-OP + operators[`add-wrap-ss] = ADD-WRAP-SS-OP + operators[`sub-wrap] = SUB-WRAP-OP + operators[`sub-wrap-uu] = SUB-WRAP-UU-OP + operators[`sub-wrap-us] = SUB-WRAP-US-OP + operators[`sub-wrap-su] = SUB-WRAP-SU-OP + operators[`sub-wrap-ss] = SUB-WRAP-SS-OP operators[`less] = LESS-OP + operators[`less-uu] = LESS-UU-OP + operators[`less-us] = LESS-US-OP + operators[`less-su] = LESS-SU-OP + operators[`less-ss] = LESS-SS-OP operators[`less-eq] = LESS-EQ-OP + operators[`less-eq-uu] = LESS-EQ-UU-OP + operators[`less-eq-us] = LESS-EQ-US-OP + operators[`less-eq-su] = LESS-EQ-SU-OP + operators[`less-eq-ss] = LESS-EQ-SS-OP operators[`greater] = GREATER-OP + operators[`greater-uu] = GREATER-UU-OP + operators[`greater-us] = GREATER-US-OP + operators[`greater-su] = GREATER-SU-OP + operators[`greater-ss] = GREATER-SS-OP operators[`greater-eq] = GREATER-EQ-OP + operators[`greater-eq-uu] = GREATER-EQ-UU-OP + operators[`greater-eq-us] = GREATER-EQ-US-OP + operators[`greater-eq-su] = GREATER-EQ-SU-OP + operators[`greater-eq-ss] = GREATER-EQ-SS-OP operators[`equal] = EQUAL-OP - operators[`multiplex] = MULTIPLEX-OP + operators[`equal-uu] = EQUAL-UU-OP + operators[`equal-ss] = EQUAL-SS-OP + operators[`mux] = MUX-OP + operators[`mux-uu] = MUX-UU-OP + operators[`mux-ss] = MUX-SS-OP operators[`pad] = PAD-OP + operators[`pad-u] = PAD-U-OP + operators[`pad-s] = PAD-S-OP + operators[`as-UInt] = AS-UINT-OP + operators[`as-UInt-u] = AS-UINT-U-OP + operators[`as-UInt-s] = AS-UINT-S-OP + operators[`as-SInt] = AS-SINT-OP + operators[`as-SInt-u] = AS-SINT-U-OP + operators[`as-SInt-s] = AS-SINT-S-OP operators[`shift-left] = SHIFT-LEFT-OP + operators[`shift-left-u] = SHIFT-LEFT-U-OP + operators[`shift-left-s] = SHIFT-LEFT-S-OP operators[`shift-right] = SHIFT-RIGHT-OP + operators[`shift-right-u] = SHIFT-RIGHT-U-OP + operators[`shift-right-s] = SHIFT-RIGHT-S-OP + operators[`convert] = SHIFT-RIGHT-OP + operators[`convert-u] = SHIFT-RIGHT-U-OP + operators[`convert-s] = SHIFT-RIGHT-S-OP + operators[`bit-and] = BIT-AND-OP + operators[`bit-or] = BIT-OR-OP + operators[`bit-xor] = BIT-XOR-OP + operators[`concat] = CONCAT-OP operators[`bit] = BIT-SELECT-OP operators[`bits] = BITS-SELECT-OP diff --git a/src/main/stanza/ir-utils.stanza b/src/main/stanza/ir-utils.stanza index 1aaa264a..4da64981 100644 --- a/src/main/stanza/ir-utils.stanza +++ b/src/main/stanza/ir-utils.stanza @@ -25,27 +25,100 @@ defmethod print (o:OutputStream, op:PrimOp) : print{o, _} $ switch {op == _} : ADD-OP : "add" - ADD-MOD-OP : "add-mod" - SUB-OP : "minus" - SUB-MOD-OP : "sub-mod" - TIMES-OP : "times" - DIVIDE-OP : "divide" + ADD-UU-OP : "add-uu" + ADD-US-OP : "add-us" + ADD-SU-OP : "add-su" + ADD-SS-OP : "add-ss" + SUB-OP : "sub" + SUB-UU-OP : "sub-uu" + SUB-US-OP : "sub-us" + SUB-SU-OP : "sub-su" + SUB-SS-OP : "sub-ss" + MUL-OP : "mul" + MUL-UU-OP : "mul-uu" + MUL-US-OP : "mul-us" + MUL-SU-OP : "mul-su" + MUL-SS-OP : "mul-ss" + DIV-OP : "div" + DIV-UU-OP : "div-uu" + DIV-US-OP : "div-us" + DIV-SU-OP : "div-su" + DIV-SS-OP : "div-ss" MOD-OP : "mod" + MOD-UU-OP : "mod-uu" + MOD-US-OP : "mod-us" + MOD-SU-OP : "mod-su" + MOD-SS-OP : "mod-ss" + QUO-OP : "quo" + QUO-UU-OP : "quo-uu" + QUO-US-OP : "quo-us" + QUO-SU-OP : "quo-su" + QUO-SS-OP : "quo-ss" + REM-OP : "rem" + REM-UU-OP : "rem-uu" + REM-US-OP : "rem-us" + REM-SU-OP : "rem-su" + REM-SS-OP : "rem-ss" + ADD-WRAP-OP : "add-wrap" + ADD-WRAP-UU-OP : "add-wrap-uu" + ADD-WRAP-US-OP : "add-wrap-us" + ADD-WRAP-SU-OP : "add-wrap-su" + ADD-WRAP-SS-OP : "add-wrap-ss" + SUB-WRAP-OP : "sub-wrap" + SUB-WRAP-UU-OP : "sub-wrap-uu" + SUB-WRAP-US-OP : "sub-wrap-us" + SUB-WRAP-SU-OP : "sub-wrap-su" + SUB-WRAP-SS-OP : "sub-wrap-ss" + LESS-OP : "less" + LESS-UU-OP : "less-uu" + LESS-US-OP : "less-us" + LESS-SU-OP : "less-su" + LESS-SS-OP : "less-ss" + LESS-EQ-OP : "less-eq" + LESS-EQ-UU-OP : "less-eq-uu" + LESS-EQ-US-OP : "less-eq-us" + LESS-EQ-SU-OP : "less-eq-su" + LESS-EQ-SS-OP : "less-eq-ss" + GREATER-OP : "greater" + GREATER-UU-OP : "greater-uu" + GREATER-US-OP : "greater-us" + GREATER-SU-OP : "greater-su" + GREATER-SS-OP : "greater-ss" + GREATER-EQ-OP : "greater-eq" + GREATER-EQ-UU-OP : "greater-eq-uu" + GREATER-EQ-US-OP : "greater-eq-us" + GREATER-EQ-SU-OP : "greater-eq-su" + GREATER-EQ-SS-OP : "greater-eq-ss" + EQUAL-OP : "equal" + EQUAL-UU-OP : "equal-uu" + EQUAL-SS-OP : "equal-ss" + MUX-OP : "mux" + MUX-UU-OP : "mux-uu" + MUX-SS-OP : "mux-ss" + PAD-OP : "pad" + PAD-U-OP : "pad-u" + PAD-S-OP : "pad-s" + AS-UINT-OP : "as-UInt" + AS-UINT-U-OP : "as-UInt-u" + AS-UINT-S-OP : "as-UInt-s" + AS-SINT-OP : "as-SInt" + AS-SINT-U-OP : "as-SInt-u" + AS-SINT-S-OP : "as-SInt-s" SHIFT-LEFT-OP : "shift-left" + SHIFT-LEFT-U-OP : "shift-left-u" + SHIFT-LEFT-S-OP : "shift-left-s" SHIFT-RIGHT-OP : "shift-right" - PAD-OP : "pad" + SHIFT-RIGHT-U-OP : "shift-right-u" + SHIFT-RIGHT-S-OP : "shift-right-s" + CONVERT-OP : "convert" + CONVERT-U-OP : "convert-u" + CONVERT-S-OP : "convert-s" BIT-AND-OP : "bit-and" BIT-OR-OP : "bit-or" BIT-XOR-OP : "bit-xor" CONCAT-OP : "concat" - BIT-SELECT-OP : "bit-select" - BITS-SELECT-OP : "bits-select" - MULTIPLEX-OP : "multiplex" - LESS-OP : "less" - LESS-EQ-OP : "less-eq" - GREATER-OP : "greater" - GREATER-EQ-OP : "greater-eq" - EQUAL-OP : "equal" + BIT-SELECT-OP : "bit" + BITS-SELECT-OP : "bits" defmethod print (o:OutputStream, e:Expression) : match(e) : diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza index ede24603..18593499 100644 --- a/src/main/stanza/passes.stanza +++ b/src/main/stanza/passes.stanza @@ -343,107 +343,119 @@ defn initialize-registers (c:Circuit) : ; postponed for a later/earlier pass. defn get-primop-rettype (e:DoPrim) -> Type : - defn u() = UIntType(UnknownWidth()) - defn s() = SIntType(UnknownWidth()) - match(e) : - (e:ADD-OP ) : u() - (e:ADD-UU-OP ) : u() - (e:ADD-US-OP ) : s() - (e:ADD-SU-OP ) : s() - (e:ADD-SS-OP ) : s() - (e:SUB-OP ) : s() - (e:SUB-UU-OP ) : s() - (e:SUB-US-OP ) : s() - (e:SUB-SU-OP ) : s() - (e:SUB-SS-OP ) : s() - (e:TIMES-OP ) : u() - (e:TIMES-UU-OP ) : u() - (e:TIMES-US-OP ) : s() - (e:TIMES-SU-OP ) : s() - (e:TIMES-SS-OP ) : s() - (e:DIVIDE-OP ) : u() - (e:DIVIDE-UU-OP ) : u() - (e:DIVIDE-US-OP ) : s() - (e:DIVIDE-SU-OP ) : s() - (e:DIVIDE-SS-OP ) : s() - (e:MOD-OP ) : u() - (e:MOD-UU-OP ) : s() - (e:MOD-US-OP ) : s() - (e:MOD-SU-OP ) : s() - (e:MOD-SS-OP ) : s() - (e:QUOTIENT-OP ) : u() - (e:QUOTIENT-UU-OP ) : u() - (e:QUOTIENT-US-OP ) : s() - (e:QUOTIENT-SU-OP ) : s() - (e:QUOTIENT-SS-OP ) : s() - (e:REMAINDER-OP ) : u() - (e:REMAINDER-UU-OP ) : u() - (e:REMAINDER-US-OP ) : s() - (e:REMAINDER-SU-OP ) : u() - (e:REMAINDER-SS-OP ) : s() - (e:ADD-WRAP-OP ) : u() - (e:ADD-WRAP-UU-OP ) : u() - (e:ADD-WRAP-US-OP ) : s() - (e:ADD-WRAP-SU-OP ) : s() - (e:ADD-WRAP-SS-OP ) : s() - (e:SUB-WRAP-OP ) : u() - (e:SUB-WRAP-UU-OP ) : u() - (e:SUB-WRAP-US-OP ) : s() - (e:SUB-WRAP-SU-OP ) : s() - (e:SUB-WRAP-SS-OP ) : s() - (e:LESS-OP ) : u() - (e:LESS-UU-OP ) : u() - (e:LESS-US-OP ) : u() - (e:LESS-SU-OP ) : u() - (e:LESS-SS-OP ) : u() - (e:LESS-EQ-OP ) : u() - (e:LESS-EQ-UU-OP ) : u() - (e:LESS-EQ-US-OP ) : u() - (e:LESS-EQ-SU-OP ) : u() - (e:LESS-EQ-SS-OP ) : u() - (e:GREATER-OP ) : u() - (e:GREATER-UU-OP ) : u() - (e:GREATER-US-OP ) : u() - (e:GREATER-SU-OP ) : u() - (e:GREATER-SS-OP ) : u() - (e:GREATER-EQ-OP ) : u() - (e:GREATER-EQ-UU-OP ) : u() - (e:GREATER-EQ-US-OP ) : u() - (e:GREATER-EQ-SU-OP ) : u() - (e:GREATER-EQ-SS-OP ) : u() - (e:EQUAL-OP ) : u() - (e:EQUAL-UU-OP ) : u() - (e:EQUAL-SS-OP ) : u() - (e:MULTIPLEX-OP ) : u() - (e:MULTIPLEX-UU-OP ) : u() - (e:MULTIPLEX-SS-OP ) : s() - (e:PAD-OP ) : u() - (e:PAD-U-OP ) : u() - (e:PAD-S-OP ) : s() - (e:AS-UINT-OP ) : u() - (e:AS-UINT-U-OP ) : u() - (e:AS-UINT-S-OP ) : u() - (e:AS-SINT-OP ) : s() - (e:AS-SINT-U-OP ) : s() - (e:AS-SINT-S-OP ) : s() - (e:SHIFT-LEFT-OP ) : u() - (e:SHIFT-LEFT-U-OP ) : u() - (e:SHIFT-LEFT-S-OP ) : s() - (e:SHIFT-RIGHT-OP ) : u() - (e:SHIFT-RIGHT-U-OP ) : u() - (e:SHIFT-RIGHT-S-OP ) : s() - (e:CONVERT-OP ) : u() - (e:CONVERT-U-OP ) : u() - (e:CONVERT-S-OP ) : u() - (e:BIT-AND-OP ) : u() - (e:BIT-OR-OP ) : u() - (e:BIT-XOR-OP ) : u() - (e:CONCAT-OP ) : u() - (e:BIT-SELECT-OP ) : u() - (e:BITS-SELECT-OP ) : u() + defn u () : UIntType(UnknownWidth()) + defn s () : SIntType(UnknownWidth()) + defn u-and (op1:Expression,op2:Expression) : + if type(op1) typeof UIntType and type(op2) typeof UIntType : + UIntType(UnknownWidth()) + else : + SIntType(UnknownWidth()) + defn of-type (op:Expression) : + if type(op) typeof UIntType : + UIntType(UnknownWidth()) + if type(op) typeof SIntType : + SIntType(UnknownWidth()) + else : UnknownType() + + switch {e == _} : + ADD-OP : u-and(args(e)[0],args(e)[1]) + ADD-UU-OP : u() + ADD-US-OP : s() + ADD-SU-OP : s() + ADD-SS-OP : s() + SUB-OP : s() + SUB-UU-OP : s() + SUB-US-OP : s() + SUB-SU-OP : s() + SUB-SS-OP : s() + MUL-OP : u-and(args(e)[0],args(e)[1]) + MUL-UU-OP : u() + MUL-US-OP : s() + MUL-SU-OP : s() + MUL-SS-OP : s() + DIV-OP : u-and(args(e)[0],args(e)[1]) + DIV-UU-OP : u() + DIV-US-OP : s() + DIV-SU-OP : s() + DIV-SS-OP : s() + MOD-OP : u() + MOD-UU-OP : u() + MOD-US-OP : u() + MOD-SU-OP : u() + MOD-SS-OP : u() + QUO-OP : u-and(args(e)[0],args(e)[1]) + QUO-UU-OP : u() + QUO-US-OP : s() + QUO-SU-OP : s() + QUO-SS-OP : s() + REM-OP : of-type(args(e)[1]) + REM-UU-OP : u() + REM-US-OP : s() + REM-SU-OP : u() + REM-SS-OP : s() + ADD-WRAP-OP : u-and(args(e)[0],args(e)[1]) + ADD-WRAP-UU-OP : u() + ADD-WRAP-US-OP : s() + ADD-WRAP-SU-OP : s() + ADD-WRAP-SS-OP : s() + SUB-WRAP-OP : u-and(args(e)[0],args(e)[1]) + SUB-WRAP-UU-OP : u() + SUB-WRAP-US-OP : s() + SUB-WRAP-SU-OP : s() + SUB-WRAP-SS-OP : s() + LESS-OP : u() + LESS-UU-OP : u() + LESS-US-OP : u() + LESS-SU-OP : u() + LESS-SS-OP : u() + LESS-EQ-OP : u() + LESS-EQ-UU-OP : u() + LESS-EQ-US-OP : u() + LESS-EQ-SU-OP : u() + LESS-EQ-SS-OP : u() + GREATER-OP : u() + GREATER-UU-OP : u() + GREATER-US-OP : u() + GREATER-SU-OP : u() + GREATER-SS-OP : u() + GREATER-EQ-OP : u() + GREATER-EQ-UU-OP : u() + GREATER-EQ-US-OP : u() + GREATER-EQ-SU-OP : u() + GREATER-EQ-SS-OP : u() + EQUAL-OP : u() + EQUAL-UU-OP : u() + EQUAL-SS-OP : u() + MUX-OP : of-type(args(e)[0]) + MUX-UU-OP : u() + MUX-SS-OP : s() + PAD-OP : of-type(args(e)[0]) + PAD-U-OP : u() + PAD-S-OP : s() + AS-UINT-OP : u() + AS-UINT-U-OP : u() + AS-UINT-S-OP : u() + AS-SINT-OP : s() + AS-SINT-U-OP : s() + AS-SINT-S-OP : s() + SHIFT-LEFT-OP : of-type(args(e)[0]) + SHIFT-LEFT-U-OP : u() + SHIFT-LEFT-S-OP : s() + SHIFT-RIGHT-OP : of-type(args(e)[0]) + SHIFT-RIGHT-U-OP : u() + SHIFT-RIGHT-S-OP : s() + CONVERT-OP : s() + CONVERT-U-OP : s() + CONVERT-S-OP : s() + BIT-AND-OP : u() + BIT-OR-OP : u() + BIT-XOR-OP : u() + CONCAT-OP : u() + BIT-SELECT-OP : u() + BITS-SELECT-OP : u() defn type (m:Module) -> Type : - BundleType(ports(module(s))) + BundleType(ports(m)) defn get-type (b:Symbol,l:List<KeyValue<Symbol,Type>>) -> Type : val contains? = for kv in l any? : b == key(kv) @@ -451,9 +463,10 @@ defn get-type (b:Symbol,l:List<KeyValue<Symbol,Type>>) -> Type : label<Type> myret : for kv in l do : if b == key(kv) : myret(value(kv)) + myret(UnknownType()) else : UnknownType() -defn get-bundle-subtype (v:Type,s:Symbol) -> Type : +defn bundle-field-type (v:Type,s:Symbol) -> Type : match(v) : (v:BundleType) : val contains? = for p in ports(v) any? : name(p) == s @@ -471,15 +484,15 @@ defn get-vector-subtype (v:Type) -> Type : defn infer-types (e:Expression, l:List<KeyValue<Symbol,Type>>) -> Expression : match(map(infer-types{_,l},e)) : - (e:WRef) : WRef(name(e), get-type(name(e),l)) - (e:WField) : WField(exp(e),name(e), get-bundle-subtype(type(exp(e)))) - (e:WIndex) : WIndex(exp(e),name(e), get-vector-subtype(type(exp(e)))) + (e:WRef) : WRef(name(e), get-type(name(e),l),kind(e),dir(e)) + (e:WField) : WField(exp(e),name(e), bundle-field-type(type(exp(e)),name(e)),dir(e)) + (e:WIndex) : WIndex(exp(e),value(e), get-vector-subtype(type(exp(e))),dir(e)) (e:DoPrim) : DoPrim(op(e),args(e),consts(e),get-primop-rettype(e)) (e:ReadPort) : ReadPort(mem(e),index(e),get-vector-subtype(type(mem(e)))) (e:UIntValue|SIntValue|Null) : e -defn infer-types (s:Stmt, l:List<KeyValue<Symbol,Type>>) -> [Stmt, List<KeyValue<Symbol,Type>>] - match(map(infer-types{_,l},s)) : +defn infer-types (s:Stmt, l:List<KeyValue<Symbol,Type>>) -> [Stmt, List<KeyValue<Symbol,Type>>] : + match(s) : (s:LetRec) : [s,l] ;TODO, this is wrong but we might be getting rid of letrecs? (s:Begin) : var env = l @@ -489,17 +502,24 @@ defn infer-types (s:Stmt, l:List<KeyValue<Symbol,Type>>) -> [Stmt, List<KeyValue env = l* s* [Begin(body*),env] - (s:DefWire|DefRegister|DefMemory) : [s,List(name(s) => type(s),l)] + (s:DefWire) : [s,List(name(s) => type(s),l)] + (s:DefRegister) : [s,List(name(s) => type(s),l)] + (s:DefMemory) : [s,List(name(s) => type(s),l)] (s:DefInstance) : [s, List(name(s) => type(module(s)),l)] (s:DefNode) : [s, List(name(s) => type(value(s)),l)] (s:WDefAccessor) : [s, List(name(s) => type(source(s)),l)] - (s:Conditionally|Connect|EmptyStmt) : [s,l] + (s:Conditionally) : + val [s*,l*] = infer-types(conseq(s),l) + val [s**,l**] = infer-types(alt(s),l) + [Conditionally(pred(s),s*,s**),l] + (s:Connect|EmptyStmt) : [s,l] defn infer-types (m:Module, l:List<KeyValue<Symbol,Type>>) -> Module : val ptypes = for p in ports(m) map : name(p) => type(p) - infer-types(body(m),append(ptypes, l)) + val [s,l*] = infer-types(body(m),append(ptypes, l)) + Module(name(m),ports(m),s) defn infer-types (c:Circuit) -> Circuit : val l = @@ -521,6 +541,10 @@ defn times (d1:Direction, d2:Direction) : if d1 == INPUT : flip(d2) else : d2 +defn lookup-port (ports: Streamable<Port>, port-name: Symbol) : + for port in ports find : + name(port) == port-name + defn bundle-field-dir (t:Type, n:Symbol) -> Direction : match(t) : (t:BundleType) : @@ -1044,7 +1068,7 @@ defn expand-whens (m:Module) : exp(sv) (sv:WhenValue) : defn multiplex-exp (pred:Expression, conseq:Expression, alt:Expression) : - DoPrim(MULTIPLEX-OP, list(pred, conseq, alt), List(), type(conseq)) + DoPrim(MUX-OP, list(pred, conseq, alt), List(), type(conseq)) multiplex-exp(pred(sv), convert-symbolic(key, conseq(sv)) convert-symbolic(key, alt(sv))) @@ -1229,11 +1253,11 @@ defn primop-width (op:PrimOp, ws:List<Width>, ints:List<Int>) -> Exp : switch {op == _} : ADD-OP : wmax-inc(ws[0], ws[1]) - ADD-MOD-OP : wmax(ws[0], ws[1]) + ADD-WRAP-OP : wmax(ws[0], ws[1]) SUB-OP : wmax-inc(ws[0], ws[1]) - SUB-MOD-OP : wmax(ws[0], ws[1]) - TIMES-OP : wplus(ws[0], ws[1]) - DIVIDE-OP : wminus(ws[0], ws[1]) + SUB-WRAP-OP : wmax(ws[0], ws[1]) + MUL-OP : wplus(ws[0], ws[1]) + DIV-OP : wminus(ws[0], ws[1]) MOD-OP : to-exp(ws[1]) SHIFT-LEFT-OP : wplus(ws[0], ints[0]) SHIFT-RIGHT-OP : wminus(ws[0], ints[0]) @@ -1244,7 +1268,7 @@ defn primop-width (op:PrimOp, ws:List<Width>, ints:List<Int>) -> Exp : CONCAT-OP : wplus(ws[0], ints[0]) BIT-SELECT-OP : ELit(1) BITS-SELECT-OP : ELit(ints[0]) - MULTIPLEX-OP : wmax(ws[1], ws[2]) + MUX-OP : wmax(ws[1], ws[2]) LESS-OP : ELit(1) LESS-EQ-OP : ELit(1) GREATER-OP : ELit(1) @@ -1489,7 +1513,7 @@ defn pad-widths (c:Circuit) : if contains?([BIT-AND-OP, BIT-OR-OP, BIT-XOR-OP, EQUAL-OP], op(e)) : val args* = match-widths(args(e)) DoPrim(op(e), args*, consts(e), type(e)) - else if op(e) == MULTIPLEX-OP : + else if op(e) == MUX-OP : val args* = List(head(args(e)), match-widths(tail(args(e)))) DoPrim(op(e), args*, consts(e), type(e)) else : @@ -1822,8 +1846,8 @@ defn inline-instances (c:Circuit) : ;; ADD-MOD-OP : "add" ;; MINUS-OP : "sub" ;; SUB-MOD-OP : "sub" -;; TIMES-OP : "mul" ;; todo: signed version -;; DIVIDE-OP : "div" ;; todo: signed version +;; MUL-OP : "mul" ;; todo: signed version +;; DIV-OP : "div" ;; todo: signed version ;; MOD-OP : "mod" ;; todo: signed version ;; SHIFT-LEFT-OP : "lsh" ;; todo: signed version ;; SHIFT-RIGHT-OP : "rsh" @@ -1839,7 +1863,7 @@ defn inline-instances (c:Circuit) : ;; GREATER-OP : "gt" ;; todo: swap args ;; GREATER-EQ-OP : "gte" ;; todo: signed version ;; EQUAL-OP : "eq" -;; MULTIPLEX-OP : "mux" +;; MUX-OP : "mux" ;; else : error $ string-join $ ;; ["Unable to print Primop: " op] ;; |
