Have AppendInfo use MultiInfo, rather than appending with : (#1580)

* Bugfix - have AppendInfo use MultiInfo, rather than appending with :

* Address reviewer feedback

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

2 files changed, 22 insertions, 4 deletions

diff --git a/src/main/scala/firrtl/Visitor.scala b/src/main/scala/firrtl/Visitor.scala
index 084a3006..4033c0fd 100644
--- a/src/main/scala/firrtl/Visitor.scala
+++ b/src/main/scala/firrtl/Visitor.scala
@@ -60,7 +60,7 @@ class Visitor(infoMode: InfoMode) extends AbstractParseTreeVisitor[FirrtlNode] w
 
   private def visitInfo(ctx: Option[InfoContext], parentCtx: ParserRuleContext): Info = {
     def genInfo(filename: String): String =
-      stripPath(filename) + "@" + parentCtx.getStart.getLine + "." +
+      stripPath(filename) + " " + parentCtx.getStart.getLine + ":" +
         parentCtx.getStart.getCharPositionInLine
     lazy val useInfo: String = ctx match {
       case Some(info) => info.getText.drop(2).init // remove surrounding @[ ... ]
@@ -70,9 +70,12 @@ class Visitor(infoMode: InfoMode) extends AbstractParseTreeVisitor[FirrtlNode] w
       case UseInfo =>
         if (useInfo.length == 0) NoInfo
         else ir.FileInfo(ir.StringLit.unescape(useInfo))
+      case AppendInfo(filename) if (useInfo.length == 0) =>
+        ir.FileInfo(ir.StringLit.unescape(genInfo(filename)))
       case AppendInfo(filename) =>
-        val newInfo = useInfo + ":" + genInfo(filename)
-        ir.FileInfo(ir.StringLit.unescape(newInfo))
+        val useFileInfo = ir.FileInfo(ir.StringLit.unescape(useInfo))
+        val newFileInfo = ir.FileInfo(ir.StringLit.unescape(genInfo(filename)))
+        ir.MultiInfo(useFileInfo, newFileInfo)
       case GenInfo(filename) =>
         ir.FileInfo(ir.StringLit.unescape(genInfo(filename)))
       case IgnoreInfo => NoInfo
diff --git a/src/test/scala/firrtlTests/InfoSpec.scala b/src/test/scala/firrtlTests/InfoSpec.scala
index 0a95b462..12ba9151 100644
--- a/src/test/scala/firrtlTests/InfoSpec.scala
+++ b/src/test/scala/firrtlTests/InfoSpec.scala
@@ -6,8 +6,9 @@ import firrtl._
 import firrtl.ir._
 import firrtl.testutils._
 import FirrtlCheckers._
+import firrtl.Parser.AppendInfo
 
-class InfoSpec extends FirrtlFlatSpec {
+class InfoSpec extends FirrtlFlatSpec with FirrtlMatchers {
   def compile(input: String): CircuitState =
     (new VerilogCompiler).compileAndEmit(CircuitState(parse(input), ChirrtlForm), List.empty)
   def compileBody(body: String) = {
@@ -158,4 +159,18 @@ class InfoSpec extends FirrtlFlatSpec {
     result should containLine ("x <= _GEN_2 @[GCD.scala 17:22 GCD.scala 19:19]")
     result should containLine ("y <= _GEN_3 @[GCD.scala 18:22 GCD.scala 19:30]")
   }
+
+  "source locators for append option" should "use multiinfo" in {
+    val input = """circuit Top :
+                  |  module Top :
+                  |    input clock : Clock
+                  |    input in: UInt<32>
+                  |    output out: UInt<32>
+                  |    out <= in @[Top.scala 15:14]
+                  |""".stripMargin
+    val circuit = firrtl.Parser.parse(input.split("\n").toIterator, AppendInfo("myfile.fir"))
+    val circuitState = CircuitState(circuit, UnknownForm)
+    val expectedInfos = Seq(FileInfo(StringLit("Top.scala 15:14")), FileInfo(StringLit("myfile.fir 6:4")))
+    circuitState should containTree { case MultiInfo(`expectedInfos`) => true }
+  }
 }