diff options
| author | azidar | 2016-07-28 13:57:30 -0700 |
|---|---|---|
| committer | azidar | 2016-07-28 13:57:30 -0700 |
| commit | 202f5201620625b60e1179421687caf55a20e2af (patch) | |
| tree | 97187b928ab9eae04ebe359b5f3a002d5309a763 /src | |
| parent | 9b1eed8fb94b222c4cbce64379995ddc3930210a (diff) | |
InferWidths now only fixes declaration widths
Then calls InferTypes to propagate inferred widths to expressions.
Required upgrading InferTypes to do simple width propagation.
Fixes #206 and #200.
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/scala/firrtl/LoweringCompilers.scala | 6 | ||||
| -rw-r--r-- | src/main/scala/firrtl/PrimOps.scala | 575 | ||||
| -rw-r--r-- | src/main/scala/firrtl/Utils.scala | 3 | ||||
| -rw-r--r-- | src/main/scala/firrtl/passes/Passes.scala | 13 |
4 files changed, 308 insertions, 289 deletions
diff --git a/src/main/scala/firrtl/LoweringCompilers.scala b/src/main/scala/firrtl/LoweringCompilers.scala index 8beaf7f9..6450aa66 100644 --- a/src/main/scala/firrtl/LoweringCompilers.scala +++ b/src/main/scala/firrtl/LoweringCompilers.scala @@ -111,9 +111,9 @@ class HighFirrtlToMiddleFirrtl () extends Transform with SimpleRun { passes.ConstProp, passes.ResolveKinds, passes.InferTypes, - passes.ResolveGenders) - //passes.InferWidths, - //passes.CheckWidths) + passes.ResolveGenders, + passes.InferWidths, + passes.CheckWidths) def execute (circuit: Circuit, annotationMap: AnnotationMap): TransformResult = run(circuit, passSeq) } diff --git a/src/main/scala/firrtl/PrimOps.scala b/src/main/scala/firrtl/PrimOps.scala index 7d7524f6..1bf8947a 100644 --- a/src/main/scala/firrtl/PrimOps.scala +++ b/src/main/scala/firrtl/PrimOps.scala @@ -28,6 +28,7 @@ MODIFICATIONS. package firrtl import firrtl.ir._ +import firrtl.Utils.{max, min, pow_minus_one} import com.typesafe.scalalogging.LazyLogging @@ -111,11 +112,26 @@ object PrimOps extends LazyLogging { // Borrowed from Stanza implementation def set_primop_type (e:DoPrim) : DoPrim = { //println-all(["Inferencing primop type: " e]) - def PLUS (w1:Width,w2:Width) : Width = PlusWidth(w1,w2) - def MAX (w1:Width,w2:Width) : Width = MaxWidth(Seq(w1,w2)) - def MINUS (w1:Width,w2:Width) : Width = MinusWidth(w1,w2) - def POW (w1:Width) : Width = ExpWidth(w1) - def MIN (w1:Width,w2:Width) : Width = MinWidth(Seq(w1,w2)) + def PLUS (w1:Width,w2:Width) : Width = (w1, w2) match { + case (IntWidth(i), IntWidth(j)) => IntWidth(i + j) + case _ => PlusWidth(w1,w2) + } + def MAX (w1:Width,w2:Width) : Width = (w1, w2) match { + case (IntWidth(i), IntWidth(j)) => IntWidth(max(i,j)) + case _ => MaxWidth(Seq(w1,w2)) + } + def MINUS (w1:Width,w2:Width) : Width = (w1, w2) match { + case (IntWidth(i), IntWidth(j)) => IntWidth(i - j) + case _ => MinusWidth(w1,w2) + } + def POW (w1:Width) : Width = w1 match { + case IntWidth(i) => IntWidth(pow_minus_one(BigInt(2), i)) + case _ => ExpWidth(w1) + } + def MIN (w1:Width,w2:Width) : Width = (w1, w2) match { + case (IntWidth(i), IntWidth(j)) => IntWidth(min(i,j)) + case _ => MinWidth(Seq(w1,w2)) + } val o = e.op val a = e.args val c = e.consts @@ -127,282 +143,279 @@ object PrimOps extends LazyLogging { def w3 () = Utils.widthBANG(a(2).tpe) def c1 () = IntWidth(c(0)) def c2 () = IntWidth(c(1)) - e.tpe match { - case UIntType(IntWidth(w)) => e - case SIntType(IntWidth(w)) => e - case _ => o match { - case Add => { - val t = (t1(),t2()) match { - case (t1:UIntType, t2:UIntType) => UIntType(PLUS(MAX(w1(),w2()),Utils.ONE)) - case (t1:UIntType, t2:SIntType) => SIntType(PLUS(MAX(w1(),w2()),Utils.ONE)) - case (t1:SIntType, t2:UIntType) => SIntType(PLUS(MAX(w1(),w2()),Utils.ONE)) - case (t1:SIntType, t2:SIntType) => SIntType(PLUS(MAX(w1(),w2()),Utils.ONE)) - case (t1, t2) => UnknownType - } - DoPrim(o,a,c,t) - } - case Sub => { - val t = (t1(),t2()) match { - case (t1:UIntType, t2:UIntType) => SIntType(PLUS(MAX(w1(),w2()),Utils.ONE)) - case (t1:UIntType, t2:SIntType) => SIntType(PLUS(MAX(w1(),w2()),Utils.ONE)) - case (t1:SIntType, t2:UIntType) => SIntType(PLUS(MAX(w1(),w2()),Utils.ONE)) - case (t1:SIntType, t2:SIntType) => SIntType(PLUS(MAX(w1(),w2()),Utils.ONE)) - case (t1, t2) => UnknownType - } - DoPrim(o,a,c,t) - } - case Mul => { - val t = (t1(),t2()) match { - case (t1:UIntType, t2:UIntType) => UIntType(PLUS(w1(),w2())) - case (t1:UIntType, t2:SIntType) => SIntType(PLUS(w1(),w2())) - case (t1:SIntType, t2:UIntType) => SIntType(PLUS(w1(),w2())) - case (t1:SIntType, t2:SIntType) => SIntType(PLUS(w1(),w2())) - case (t1, t2) => UnknownType - } - DoPrim(o,a,c,t) - } - case Div => { - val t = (t1(),t2()) match { - case (t1:UIntType, t2:UIntType) => UIntType(w1()) - case (t1:UIntType, t2:SIntType) => SIntType(PLUS(w1(),Utils.ONE)) - case (t1:SIntType, t2:UIntType) => SIntType(w1()) - case (t1:SIntType, t2:SIntType) => SIntType(PLUS(w1(),Utils.ONE)) - case (t1, t2) => UnknownType - } - DoPrim(o,a,c,t) - } - case Rem => { - val t = (t1(),t2()) match { - case (t1:UIntType, t2:UIntType) => UIntType(MIN(w1(),w2())) - case (t1:UIntType, t2:SIntType) => UIntType(MIN(w1(),w2())) - case (t1:SIntType, t2:UIntType) => SIntType(MIN(w1(),PLUS(w2(),Utils.ONE))) - case (t1:SIntType, t2:SIntType) => SIntType(MIN(w1(),w2())) - case (t1, t2) => UnknownType - } - DoPrim(o,a,c,t) - } - case Lt => { - val t = (t1(),t2()) match { - case (t1:UIntType, t2:UIntType) => Utils.BoolType - case (t1:SIntType, t2:UIntType) => Utils.BoolType - case (t1:UIntType, t2:SIntType) => Utils.BoolType - case (t1:SIntType, t2:SIntType) => Utils.BoolType - case (t1, t2) => UnknownType - } - DoPrim(o,a,c,t) - } - case Leq => { - val t = (t1(),t2()) match { - case (t1:UIntType, t2:UIntType) => Utils.BoolType - case (t1:SIntType, t2:UIntType) => Utils.BoolType - case (t1:UIntType, t2:SIntType) => Utils.BoolType - case (t1:SIntType, t2:SIntType) => Utils.BoolType - case (t1, t2) => UnknownType - } - DoPrim(o,a,c,t) - } - case Gt => { - val t = (t1(),t2()) match { - case (t1:UIntType, t2:UIntType) => Utils.BoolType - case (t1:SIntType, t2:UIntType) => Utils.BoolType - case (t1:UIntType, t2:SIntType) => Utils.BoolType - case (t1:SIntType, t2:SIntType) => Utils.BoolType - case (t1, t2) => UnknownType - } - DoPrim(o,a,c,t) - } - case Geq => { - val t = (t1(),t2()) match { - case (t1:UIntType, t2:UIntType) => Utils.BoolType - case (t1:SIntType, t2:UIntType) => Utils.BoolType - case (t1:UIntType, t2:SIntType) => Utils.BoolType - case (t1:SIntType, t2:SIntType) => Utils.BoolType - case (t1, t2) => UnknownType - } - DoPrim(o,a,c,t) - } - case Eq => { - val t = (t1(),t2()) match { - case (t1:UIntType, t2:UIntType) => Utils.BoolType - case (t1:SIntType, t2:UIntType) => Utils.BoolType - case (t1:UIntType, t2:SIntType) => Utils.BoolType - case (t1:SIntType, t2:SIntType) => Utils.BoolType - case (t1, t2) => UnknownType - } - DoPrim(o,a,c,t) - } - case Neq => { - val t = (t1(),t2()) match { - case (t1:UIntType, t2:UIntType) => Utils.BoolType - case (t1:SIntType, t2:UIntType) => Utils.BoolType - case (t1:UIntType, t2:SIntType) => Utils.BoolType - case (t1:SIntType, t2:SIntType) => Utils.BoolType - case (t1, t2) => UnknownType - } - DoPrim(o,a,c,t) - } - case Pad => { - val t = (t1()) match { - case (t1:UIntType) => UIntType(MAX(w1(),c1())) - case (t1:SIntType) => SIntType(MAX(w1(),c1())) - case (t1) => UnknownType - } - DoPrim(o,a,c,t) - } - case AsUInt => { - val t = (t1()) match { - case (t1:UIntType) => UIntType(w1()) - case (t1:SIntType) => UIntType(w1()) - case ClockType => UIntType(Utils.ONE) - case (t1) => UnknownType - } - DoPrim(o,a,c,t) - } - case AsSInt => { - val t = (t1()) match { - case (t1:UIntType) => SIntType(w1()) - case (t1:SIntType) => SIntType(w1()) - case ClockType => SIntType(Utils.ONE) - case (t1) => UnknownType - } - DoPrim(o,a,c,t) - } - case AsClock => { - val t = (t1()) match { - case (t1:UIntType) => ClockType - case (t1:SIntType) => ClockType - case ClockType => ClockType - case (t1) => UnknownType - } - DoPrim(o,a,c,t) - } - case Shl => { - val t = (t1()) match { - case (t1:UIntType) => UIntType(PLUS(w1(),c1())) - case (t1:SIntType) => SIntType(PLUS(w1(),c1())) - case (t1) => UnknownType - } - DoPrim(o,a,c,t) - } - case Shr => { - val t = (t1()) match { - case (t1:UIntType) => UIntType(MAX(MINUS(w1(),c1()),Utils.ONE)) - case (t1:SIntType) => SIntType(MAX(MINUS(w1(),c1()),Utils.ONE)) - case (t1) => UnknownType - } - DoPrim(o,a,c,t) - } - case Dshl => { - val t = (t1()) match { - case (t1:UIntType) => UIntType(PLUS(w1(),POW(w2()))) - case (t1:SIntType) => SIntType(PLUS(w1(),POW(w2()))) - case (t1) => UnknownType - } - DoPrim(o,a,c,t) - } - case Dshr => { - val t = (t1()) match { - case (t1:UIntType) => UIntType(w1()) - case (t1:SIntType) => SIntType(w1()) - case (t1) => UnknownType - } - DoPrim(o,a,c,t) - } - case Cvt => { - val t = (t1()) match { - case (t1:UIntType) => SIntType(PLUS(w1(),Utils.ONE)) - case (t1:SIntType) => SIntType(w1()) - case (t1) => UnknownType - } - DoPrim(o,a,c,t) - } - case Neg => { - val t = (t1()) match { - case (t1:UIntType) => SIntType(PLUS(w1(),Utils.ONE)) - case (t1:SIntType) => SIntType(PLUS(w1(),Utils.ONE)) - case (t1) => UnknownType - } - DoPrim(o,a,c,t) - } - case Not => { - val t = (t1()) match { - case (t1:UIntType) => UIntType(w1()) - case (t1:SIntType) => UIntType(w1()) - case (t1) => UnknownType - } - DoPrim(o,a,c,t) - } - case And => { - val t = (t1(),t2()) match { - case (_:SIntType|_:UIntType, _:SIntType|_:UIntType) => UIntType(MAX(w1(),w2())) - case (t1,t2) => UnknownType - } - DoPrim(o,a,c,t) - } - case Or => { - val t = (t1(),t2()) match { - case (_:SIntType|_:UIntType, _:SIntType|_:UIntType) => UIntType(MAX(w1(),w2())) - case (t1,t2) => UnknownType - } - DoPrim(o,a,c,t) - } - case Xor => { - val t = (t1(),t2()) match { - case (_:SIntType|_:UIntType, _:SIntType|_:UIntType) => UIntType(MAX(w1(),w2())) - case (t1,t2) => UnknownType - } - DoPrim(o,a,c,t) - } - case Andr => { - val t = (t1()) match { - case (_:UIntType|_:SIntType) => Utils.BoolType - case (t1) => UnknownType - } - DoPrim(o,a,c,t) - } - case Orr => { - val t = (t1()) match { - case (_:UIntType|_:SIntType) => Utils.BoolType - case (t1) => UnknownType - } - DoPrim(o,a,c,t) - } - case Xorr => { - val t = (t1()) match { - case (_:UIntType|_:SIntType) => Utils.BoolType - case (t1) => UnknownType - } - DoPrim(o,a,c,t) - } - case Cat => { - val t = (t1(),t2()) match { - case (_:UIntType|_:SIntType,_:UIntType|_:SIntType) => UIntType(PLUS(w1(),w2())) - case (t1, t2) => UnknownType - } - DoPrim(o,a,c,t) - } - case Bits => { - val t = (t1()) match { - case (_:UIntType|_:SIntType) => UIntType(PLUS(MINUS(c1(),c2()),Utils.ONE)) - case (t1) => UnknownType - } - DoPrim(o,a,c,t) - } - case Head => { - val t = (t1()) match { - case (_:UIntType|_:SIntType) => UIntType(c1()) - case (t1) => UnknownType - } - DoPrim(o,a,c,t) - } - case Tail => { - val t = (t1()) match { - case (_:UIntType|_:SIntType) => UIntType(MINUS(w1(),c1())) - case (t1) => UnknownType - } - DoPrim(o,a,c,t) - } - } + o match { + case Add => { + val t = (t1(),t2()) match { + case (t1:UIntType, t2:UIntType) => UIntType(PLUS(MAX(w1(),w2()),Utils.ONE)) + case (t1:UIntType, t2:SIntType) => SIntType(PLUS(MAX(w1(),w2()),Utils.ONE)) + case (t1:SIntType, t2:UIntType) => SIntType(PLUS(MAX(w1(),w2()),Utils.ONE)) + case (t1:SIntType, t2:SIntType) => SIntType(PLUS(MAX(w1(),w2()),Utils.ONE)) + case (t1, t2) => UnknownType + } + DoPrim(o,a,c,t) + } + case Sub => { + val t = (t1(),t2()) match { + case (t1:UIntType, t2:UIntType) => SIntType(PLUS(MAX(w1(),w2()),Utils.ONE)) + case (t1:UIntType, t2:SIntType) => SIntType(PLUS(MAX(w1(),w2()),Utils.ONE)) + case (t1:SIntType, t2:UIntType) => SIntType(PLUS(MAX(w1(),w2()),Utils.ONE)) + case (t1:SIntType, t2:SIntType) => SIntType(PLUS(MAX(w1(),w2()),Utils.ONE)) + case (t1, t2) => UnknownType + } + DoPrim(o,a,c,t) + } + case Mul => { + val t = (t1(),t2()) match { + case (t1:UIntType, t2:UIntType) => UIntType(PLUS(w1(),w2())) + case (t1:UIntType, t2:SIntType) => SIntType(PLUS(w1(),w2())) + case (t1:SIntType, t2:UIntType) => SIntType(PLUS(w1(),w2())) + case (t1:SIntType, t2:SIntType) => SIntType(PLUS(w1(),w2())) + case (t1, t2) => UnknownType + } + DoPrim(o,a,c,t) + } + case Div => { + val t = (t1(),t2()) match { + case (t1:UIntType, t2:UIntType) => UIntType(w1()) + case (t1:UIntType, t2:SIntType) => SIntType(PLUS(w1(),Utils.ONE)) + case (t1:SIntType, t2:UIntType) => SIntType(w1()) + case (t1:SIntType, t2:SIntType) => SIntType(PLUS(w1(),Utils.ONE)) + case (t1, t2) => UnknownType + } + DoPrim(o,a,c,t) + } + case Rem => { + val t = (t1(),t2()) match { + case (t1:UIntType, t2:UIntType) => UIntType(MIN(w1(),w2())) + case (t1:UIntType, t2:SIntType) => UIntType(MIN(w1(),w2())) + case (t1:SIntType, t2:UIntType) => SIntType(MIN(w1(),PLUS(w2(),Utils.ONE))) + case (t1:SIntType, t2:SIntType) => SIntType(MIN(w1(),w2())) + case (t1, t2) => UnknownType + } + DoPrim(o,a,c,t) + } + case Lt => { + val t = (t1(),t2()) match { + case (t1:UIntType, t2:UIntType) => Utils.BoolType + case (t1:SIntType, t2:UIntType) => Utils.BoolType + case (t1:UIntType, t2:SIntType) => Utils.BoolType + case (t1:SIntType, t2:SIntType) => Utils.BoolType + case (t1, t2) => UnknownType + } + DoPrim(o,a,c,t) + } + case Leq => { + val t = (t1(),t2()) match { + case (t1:UIntType, t2:UIntType) => Utils.BoolType + case (t1:SIntType, t2:UIntType) => Utils.BoolType + case (t1:UIntType, t2:SIntType) => Utils.BoolType + case (t1:SIntType, t2:SIntType) => Utils.BoolType + case (t1, t2) => UnknownType + } + DoPrim(o,a,c,t) + } + case Gt => { + val t = (t1(),t2()) match { + case (t1:UIntType, t2:UIntType) => Utils.BoolType + case (t1:SIntType, t2:UIntType) => Utils.BoolType + case (t1:UIntType, t2:SIntType) => Utils.BoolType + case (t1:SIntType, t2:SIntType) => Utils.BoolType + case (t1, t2) => UnknownType + } + DoPrim(o,a,c,t) + } + case Geq => { + val t = (t1(),t2()) match { + case (t1:UIntType, t2:UIntType) => Utils.BoolType + case (t1:SIntType, t2:UIntType) => Utils.BoolType + case (t1:UIntType, t2:SIntType) => Utils.BoolType + case (t1:SIntType, t2:SIntType) => Utils.BoolType + case (t1, t2) => UnknownType + } + DoPrim(o,a,c,t) + } + case Eq => { + val t = (t1(),t2()) match { + case (t1:UIntType, t2:UIntType) => Utils.BoolType + case (t1:SIntType, t2:UIntType) => Utils.BoolType + case (t1:UIntType, t2:SIntType) => Utils.BoolType + case (t1:SIntType, t2:SIntType) => Utils.BoolType + case (t1, t2) => UnknownType + } + DoPrim(o,a,c,t) + } + case Neq => { + val t = (t1(),t2()) match { + case (t1:UIntType, t2:UIntType) => Utils.BoolType + case (t1:SIntType, t2:UIntType) => Utils.BoolType + case (t1:UIntType, t2:SIntType) => Utils.BoolType + case (t1:SIntType, t2:SIntType) => Utils.BoolType + case (t1, t2) => UnknownType + } + DoPrim(o,a,c,t) + } + case Pad => { + val t = (t1()) match { + case (t1:UIntType) => UIntType(MAX(w1(),c1())) + case (t1:SIntType) => SIntType(MAX(w1(),c1())) + case (t1) => UnknownType + } + DoPrim(o,a,c,t) + } + case AsUInt => { + val t = (t1()) match { + case (t1:UIntType) => UIntType(w1()) + case (t1:SIntType) => UIntType(w1()) + case ClockType => UIntType(Utils.ONE) + case (t1) => UnknownType + } + DoPrim(o,a,c,t) + } + case AsSInt => { + val t = (t1()) match { + case (t1:UIntType) => SIntType(w1()) + case (t1:SIntType) => SIntType(w1()) + case ClockType => SIntType(Utils.ONE) + case (t1) => UnknownType + } + DoPrim(o,a,c,t) + } + case AsClock => { + val t = (t1()) match { + case (t1:UIntType) => ClockType + case (t1:SIntType) => ClockType + case ClockType => ClockType + case (t1) => UnknownType + } + DoPrim(o,a,c,t) + } + case Shl => { + val t = (t1()) match { + case (t1:UIntType) => UIntType(PLUS(w1(),c1())) + case (t1:SIntType) => SIntType(PLUS(w1(),c1())) + case (t1) => UnknownType + } + DoPrim(o,a,c,t) + } + case Shr => { + val t = (t1()) match { + case (t1:UIntType) => UIntType(MAX(MINUS(w1(),c1()),Utils.ONE)) + case (t1:SIntType) => SIntType(MAX(MINUS(w1(),c1()),Utils.ONE)) + case (t1) => UnknownType + } + DoPrim(o,a,c,t) + } + case Dshl => { + val t = (t1()) match { + case (t1:UIntType) => UIntType(PLUS(w1(),POW(w2()))) + case (t1:SIntType) => SIntType(PLUS(w1(),POW(w2()))) + case (t1) => UnknownType + } + DoPrim(o,a,c,t) + } + case Dshr => { + val t = (t1()) match { + case (t1:UIntType) => UIntType(w1()) + case (t1:SIntType) => SIntType(w1()) + case (t1) => UnknownType + } + DoPrim(o,a,c,t) + } + case Cvt => { + val t = (t1()) match { + case (t1:UIntType) => SIntType(PLUS(w1(),Utils.ONE)) + case (t1:SIntType) => SIntType(w1()) + case (t1) => UnknownType + } + DoPrim(o,a,c,t) + } + case Neg => { + val t = (t1()) match { + case (t1:UIntType) => SIntType(PLUS(w1(),Utils.ONE)) + case (t1:SIntType) => SIntType(PLUS(w1(),Utils.ONE)) + case (t1) => UnknownType + } + DoPrim(o,a,c,t) + } + case Not => { + val t = (t1()) match { + case (t1:UIntType) => UIntType(w1()) + case (t1:SIntType) => UIntType(w1()) + case (t1) => UnknownType + } + DoPrim(o,a,c,t) + } + case And => { + val t = (t1(),t2()) match { + case (_:SIntType|_:UIntType, _:SIntType|_:UIntType) => UIntType(MAX(w1(),w2())) + case (t1,t2) => UnknownType + } + DoPrim(o,a,c,t) + } + case Or => { + val t = (t1(),t2()) match { + case (_:SIntType|_:UIntType, _:SIntType|_:UIntType) => UIntType(MAX(w1(),w2())) + case (t1,t2) => UnknownType + } + DoPrim(o,a,c,t) + } + case Xor => { + val t = (t1(),t2()) match { + case (_:SIntType|_:UIntType, _:SIntType|_:UIntType) => UIntType(MAX(w1(),w2())) + case (t1,t2) => UnknownType + } + DoPrim(o,a,c,t) + } + case Andr => { + val t = (t1()) match { + case (_:UIntType|_:SIntType) => Utils.BoolType + case (t1) => UnknownType + } + DoPrim(o,a,c,t) + } + case Orr => { + val t = (t1()) match { + case (_:UIntType|_:SIntType) => Utils.BoolType + case (t1) => UnknownType + } + DoPrim(o,a,c,t) + } + case Xorr => { + val t = (t1()) match { + case (_:UIntType|_:SIntType) => Utils.BoolType + case (t1) => UnknownType + } + DoPrim(o,a,c,t) + } + case Cat => { + val t = (t1(),t2()) match { + case (_:UIntType|_:SIntType,_:UIntType|_:SIntType) => UIntType(PLUS(w1(),w2())) + case (t1, t2) => UnknownType + } + DoPrim(o,a,c,t) + } + case Bits => { + val t = (t1()) match { + case (_:UIntType|_:SIntType) => UIntType(PLUS(MINUS(c1(),c2()),Utils.ONE)) + case (t1) => UnknownType + } + DoPrim(o,a,c,t) + } + case Head => { + val t = (t1()) match { + case (_:UIntType|_:SIntType) => UIntType(c1()) + case (t1) => UnknownType + } + DoPrim(o,a,c,t) + } + case Tail => { + val t = (t1()) match { + case (_:UIntType|_:SIntType) => UIntType(MINUS(w1(),c1())) + case (t1) => UnknownType + } + DoPrim(o,a,c,t) + } + } } diff --git a/src/main/scala/firrtl/Utils.scala b/src/main/scala/firrtl/Utils.scala index 76c8e61e..9d11ca2f 100644 --- a/src/main/scala/firrtl/Utils.scala +++ b/src/main/scala/firrtl/Utils.scala @@ -74,6 +74,9 @@ object Utils extends LazyLogging { implicit def toWrappedExpression (x:Expression) = new WrappedExpression(x) def ceil_log2(x: BigInt): BigInt = (x-1).bitLength def ceil_log2(x: Int): Int = scala.math.ceil(scala.math.log(x) / scala.math.log(2)).toInt + def max(a: BigInt, b: BigInt): BigInt = if (a >= b) a else b + def min(a: BigInt, b: BigInt): BigInt = if (a >= b) b else a + def pow_minus_one(a: BigInt, b: BigInt): BigInt = a.pow(b.toInt) - 1 val gen_names = Map[String,Int]() val delin = "_" val BoolType = UIntType(IntWidth(1)) diff --git a/src/main/scala/firrtl/passes/Passes.scala b/src/main/scala/firrtl/passes/Passes.scala index 44de3542..6216d2aa 100644 --- a/src/main/scala/firrtl/passes/Passes.scala +++ b/src/main/scala/firrtl/passes/Passes.scala @@ -490,9 +490,6 @@ object InferWidths extends Pass { if(in.isEmpty) Seq(default) else in - def max(a: BigInt, b: BigInt): BigInt = if (a >= b) a else b - def min(a: BigInt, b: BigInt): BigInt = if (a >= b) b else a - def pow_minus_one(a: BigInt, b: BigInt): BigInt = a.pow(b.toInt) - 1 def solve(w: Width): Option[BigInt] = w match { case (w: VarWidth) => @@ -522,14 +519,20 @@ object InferWidths extends Pass { //println-all-debug(["WITH: " wx]) wx } + def reduce_var_widths_s (s: Statement): Statement = { + def onType(t: Type): Type = t map onType map reduce_var_widths_w + s map onType + } val modulesx = c.modules.map{ m => { val portsx = m.ports.map{ p => { Port(p.info,p.name,p.direction,mapr(reduce_var_widths_w _,p.tpe)) }} (m) match { case (m:ExtModule) => ExtModule(m.info,m.name,portsx) - case (m:Module) => mname = m.name; Module(m.info,m.name,portsx,mapr(reduce_var_widths_w _,m.body)) }}} - Circuit(c.info,modulesx,c.main) + case (m:Module) => + mname = m.name + Module(m.info,m.name,portsx,m.body map reduce_var_widths_s _) }}} + InferTypes.run(Circuit(c.info,modulesx,c.main)) } def run (c:Circuit): Circuit = { |
