Avoid repeated set construction in WiringTransform invalidates

Co-authored-by: Jack Koenig <koenig@sifive.com>
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

1 files changed, 3 insertions, 4 deletions

diff --git a/src/main/scala/firrtl/passes/wiring/WiringTransform.scala b/src/main/scala/firrtl/passes/wiring/WiringTransform.scala
index c41d3fed..2a574f47 100644
--- a/src/main/scala/firrtl/passes/wiring/WiringTransform.scala
+++ b/src/main/scala/firrtl/passes/wiring/WiringTransform.scala
@@ -7,6 +7,7 @@ import firrtl._
 import firrtl.Utils._
 import scala.collection.mutable
 import firrtl.annotations._
+import firrtl.options.Dependency
 import firrtl.stage.Forms
 
 /** A class for all exceptions originating from firrtl.passes.wiring */
@@ -43,10 +44,8 @@ class WiringTransform extends Transform with DependencyAPIMigration {
   override def optionalPrerequisites = Seq.empty
   override def dependents = Forms.MidEmitters
 
-  override def invalidates(a: Transform): Boolean = {
-    val everything = new mutable.LinkedHashSet[Dependency[Transform]] ++ Forms.VerilogOptimized
-    (everything -- Forms.MinimalHighForm)(Dependency.fromTransform(a))
-  }
+  private val invalidates = Forms.VerilogOptimized.toSet -- Forms.MinimalHighForm
+  override def invalidates(a: Transform): Boolean = invalidates(Dependency.fromTransform(a))
 
   /** Defines the sequence of Transform that should be applied */
   private def transforms(w: Seq[WiringInfo]): Seq[Transform] = Seq(