diff options
| author | Andrew Waterman | 2019-02-05 09:01:31 -0800 |
|---|---|---|
| committer | Albert Magyar | 2019-02-05 09:01:31 -0800 |
| commit | fa0a6e2cbe2a78fc231f47b5b73d870669b54ade (patch) | |
| tree | db7a12c72d5e7d1cdddf13db930f1d3cb1cc00a6 /src/test | |
| parent | 7ec7125eab13c43a49b9a26003c9e90413df3336 (diff) | |
Missed constprop opportunity (#1009)
* Enhance constant propagation across registers
* Add more elaborate test case for register const prop
Diffstat (limited to 'src/test')
| -rw-r--r-- | src/test/scala/firrtlTests/ConstantPropagationTests.scala | 55 |
1 files changed, 55 insertions, 0 deletions
diff --git a/src/test/scala/firrtlTests/ConstantPropagationTests.scala b/src/test/scala/firrtlTests/ConstantPropagationTests.scala index 8a69fcaa..ee2540e0 100644 --- a/src/test/scala/firrtlTests/ConstantPropagationTests.scala +++ b/src/test/scala/firrtlTests/ConstantPropagationTests.scala @@ -1005,6 +1005,61 @@ class ConstantPropagationIntegrationSpec extends LowTransformSpec { execute(input, check, Seq.empty) } + "Registers with constant reset and connection to the same constant" should "be replaced with that constant" in { + val input = + """circuit Top : + | module Top : + | input clock : Clock + | input reset : UInt<1> + | input cond : UInt<1> + | output z : UInt<8> + | reg r : UInt<8>, clock with : (reset => (reset, UInt<4>("hb"))) + | when cond : + | r <= UInt<4>("hb") + | z <= r""".stripMargin + val check = + """circuit Top : + | module Top : + | input clock : Clock + | input reset : UInt<1> + | input cond : UInt<1> + | output z : UInt<8> + | z <= UInt<8>("hb")""".stripMargin + execute(input, check, Seq.empty) + } + + "A register with constant reset and all connection to either itself or the same constant" should "be replaced with that constant" in { + val input = + """circuit Top : + | module Top : + | input clock : Clock + | input reset : UInt<1> + | input cmd : UInt<3> + | output z : UInt<8> + | reg r : UInt<8>, clock with : (reset => (reset, UInt<4>("h7"))) + | r <= r + | when eq(cmd, UInt<3>("h0")) : + | r <= UInt<3>("h7") + | else : + | when eq(cmd, UInt<3>("h1")) : + | r <= r + | else : + | when eq(cmd, UInt<3>("h2")) : + | r <= UInt<4>("h7") + | else : + | r <= r + | z <= r""".stripMargin + val check = + """circuit Top : + | module Top : + | input clock : Clock + | input reset : UInt<1> + | input cmd : UInt<3> + | output z : UInt<8> + | z <= UInt<8>("h7")""".stripMargin + execute(input, check, Seq.empty) + } + "Registers with ONLY constant connection" should "be replaced with that constant" in { val input = """circuit Top : |