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authorAlbert Magyar2020-03-09 20:02:06 -0700
committerAlbert Magyar2020-03-16 10:24:52 -0700
commite41936d5283ba8caae2a23602e8e1a2baea391cb (patch)
tree19e29be01e09822c44473d3184277ed24b3158f9 /src/test
parentb3d4654935db38990d6cc4976eed7ddc14cf60fd (diff)
Check for collision of defnames with Module names
* Fixes #1096
Diffstat (limited to 'src/test')
-rw-r--r--src/test/scala/firrtlTests/CheckSpec.scala17
1 files changed, 17 insertions, 0 deletions
diff --git a/src/test/scala/firrtlTests/CheckSpec.scala b/src/test/scala/firrtlTests/CheckSpec.scala
index f03b6611..aa154bab 100644
--- a/src/test/scala/firrtlTests/CheckSpec.scala
+++ b/src/test/scala/firrtlTests/CheckSpec.scala
@@ -333,6 +333,23 @@ class CheckSpec extends FlatSpec with Matchers {
}
}
+ s"Defnames that conflict with pure-FIRRTL module names" should "throw an exception" in {
+ val input =
+ s"""|circuit bar :
+ | module bar :
+ | input i : UInt<8>
+ | output o : UInt<8>
+ | o <= i
+ | extmodule dup :
+ | input i : UInt<8>
+ | output o : UInt<8>
+ | defname = bar
+ |""".stripMargin
+ assertThrows[CheckHighForm.DefnameConflictException] {
+ checkHighInput(input)
+ }
+ }
+
}
object CheckSpec {