Merge pull request #1388 from freechipsproject/allow-self-renames

Allow self renames

1 files changed, 28 insertions, 0 deletions

diff --git a/src/test/scala/firrtlTests/RenameMapSpec.scala b/src/test/scala/firrtlTests/RenameMapSpec.scala
index 2da10b7f..dc091b0a 100644
--- a/src/test/scala/firrtlTests/RenameMapSpec.scala
+++ b/src/test/scala/firrtlTests/RenameMapSpec.scala
@@ -752,4 +752,32 @@ class RenameMapSpec extends FirrtlFlatSpec {
       Some(Seq(bar2))
     }
   }
+
+  it should "record a self-rename" in {
+    val top = CircuitTarget("Top").module("Top")
+    val foo = top.instOf("foo", "Mod")
+    val bar = top.instOf("bar", "Mod")
+
+    val r = RenameMap()
+
+    r.record(foo, bar)
+    r.record(foo, foo)
+
+    r.get(foo) should not be (empty)
+    r.get(foo).get should contain allOf (foo, bar)
+  }
+
+  it should "not record the same rename multiple times" in {
+    val top = CircuitTarget("Top").module("Top")
+    val foo = top.instOf("foo", "Mod")
+    val bar = top.instOf("bar", "Mod")
+
+    val r = RenameMap()
+
+    r.record(foo, bar)
+    r.record(foo, bar)
+
+    r.get(foo) should not be (empty)
+    r.get(foo).get should contain theSameElementsAs Seq(bar)
+  }
 }