Merge pull request #1264 from freechipsproject/cleanup-verilog-emitter-casts

Cleanup verilog emitter casts

4 files changed, 192 insertions, 6 deletions

diff --git a/src/test/scala/firrtlTests/AsyncResetSpec.scala b/src/test/scala/firrtlTests/AsyncResetSpec.scala
index ed90954b..f347ec14 100644
--- a/src/test/scala/firrtlTests/AsyncResetSpec.scala
+++ b/src/test/scala/firrtlTests/AsyncResetSpec.scala
@@ -65,10 +65,10 @@ class AsyncResetSpec extends FirrtlFlatSpec {
       |z <= asAsyncReset(a)
       |""".stripMargin
     )
-    result should containLine ("assign v = $unsigned(a);")
-    result should containLine ("assign w = $signed(a);")
+    result should containLine ("assign v = a;")
+    result should containLine ("assign w = a;")
     result should containLine ("assign x = a;")
-    result should containLine ("assign y = $signed(a);")
+    result should containLine ("assign y = a;")
     result should containLine ("assign z = a;")
   }
 
diff --git a/src/test/scala/firrtlTests/ConstantPropagationTests.scala b/src/test/scala/firrtlTests/ConstantPropagationTests.scala
index 71709255..af186cda 100644
--- a/src/test/scala/firrtlTests/ConstantPropagationTests.scala
+++ b/src/test/scala/firrtlTests/ConstantPropagationTests.scala
@@ -3,8 +3,6 @@
 package firrtlTests
 
 import firrtl._
-import firrtl.ir.Circuit
-import firrtl.Parser.IgnoreInfo
 import firrtl.passes._
 import firrtl.transforms._
 
@@ -824,6 +822,30 @@ class ConstantPropagationSingleModule extends ConstantPropagationSpec {
       """.stripMargin
     (parse(exec(input))) should be(parse(check))
   }
+
+  def castCheck(tpe: String, cast: String): Unit = {
+    val input =
+     s"""circuit Top :
+        |  module Top :
+        |    input  x : $tpe
+        |    output z : $tpe
+        |    z <= $cast(x)
+      """.stripMargin
+    val check =
+     s"""circuit Top :
+        |  module Top :
+        |    input  x : $tpe
+        |    output z : $tpe
+        |    z <= x
+      """.stripMargin
+    (parse(exec(input)).serialize) should be (parse(check).serialize)
+  }
+  it should "optimize unnecessary casts" in {
+    castCheck("UInt<4>", "asUInt")
+    castCheck("SInt<4>", "asSInt")
+    castCheck("Clock", "asClock")
+    castCheck("AsyncReset", "asAsyncReset")
+  }
 }
 
 // More sophisticated tests of the full compiler
diff --git a/src/test/scala/firrtlTests/VerilogEmitterTests.scala b/src/test/scala/firrtlTests/VerilogEmitterTests.scala
index 0376a830..bb7659e9 100644
--- a/src/test/scala/firrtlTests/VerilogEmitterTests.scala
+++ b/src/test/scala/firrtlTests/VerilogEmitterTests.scala
@@ -182,6 +182,16 @@ class DoPrimVerilog extends FirrtlFlatSpec {
 }
 
 class VerilogEmitterSpec extends FirrtlFlatSpec {
+  private def compile(input: String): CircuitState =
+    (new VerilogCompiler).compileAndEmit(CircuitState(parse(input), ChirrtlForm), List.empty)
+  private def compileBody(body: String): CircuitState = {
+    val str = """
+      |circuit Test :
+      |  module Test :
+      |""".stripMargin + body.split("\n").mkString("    ", "\n    ", "")
+    compile(str)
+  }
+
   "Ports" should "emit with widths aligned and names aligned" in {
     val compiler = new VerilogCompiler
     val input =
@@ -378,7 +388,6 @@ class VerilogEmitterSpec extends FirrtlFlatSpec {
     output.circuit.serialize should be (parse(check_firrtl).serialize)
   }
 
-
   behavior of "Register Updates"
 
   they should "emit using 'else if' constructs" in {
@@ -520,6 +529,94 @@ class VerilogEmitterSpec extends FirrtlFlatSpec {
     result        should containLine ("tmp <= in_9;")
   }
 
+  "SInt addition" should "have casts" in {
+    val compiler = new VerilogCompiler
+    val result = compileBody(
+      """input x : SInt<4>
+        |input y : SInt<4>
+        |output z : SInt
+        |z <= add(x, y)
+        |""".stripMargin
+    )
+    result should containLine("assign z = $signed(x) + $signed(y);")
+  }
+
+  it should "NOT cast SInt literals" in {
+    val compiler = new VerilogCompiler
+    val result = compileBody(
+      """input x : SInt<4>
+        |output z : SInt
+        |z <= add(x, SInt(-1))
+        |""".stripMargin
+    )
+    result should containLine("assign z = $signed(x) + -4'sh1;")
+  }
+
+  it should "inline asSInt casts" in {
+    val compiler = new VerilogCompiler
+    val result = compileBody(
+      """input x : UInt<4>
+        |input y : UInt<4>
+        |output z : SInt
+        |node _T_1 = asSInt(x)
+        |z <= add(_T_1, asSInt(y))
+        |""".stripMargin
+    )
+    result should containLine("assign z = $signed(x) + $signed(y);")
+  }
+
+  "Verilog Emitter" should "drop asUInt casts on Clocks" in {
+    val compiler = new VerilogCompiler
+    val result = compileBody(
+      """input x : Clock
+        |input y : Clock
+        |output z : UInt<1>
+        |node _T_1 = asUInt(x)
+        |z <= eq(_T_1, asUInt(y))
+        |""".stripMargin
+    )
+    result should containLine("assign z = x == y;")
+  }
+
+  it should "drop asClock casts on UInts" in {
+    val compiler = new VerilogCompiler
+    val result = compileBody(
+      """input x : UInt<1>
+        |input y : UInt<1>
+        |output z : Clock
+        |node _T_1 = eq(x, y)
+        |z <= asClock(_T_1)
+        |""".stripMargin
+    )
+    result should containLine("assign z = x == y;")
+  }
+
+  it should "drop asUInt casts on AsyncResets" in {
+    val compiler = new VerilogCompiler
+    val result = compileBody(
+      """input x : AsyncReset
+        |input y : AsyncReset
+        |output z : UInt<1>
+        |node _T_1 = asUInt(x)
+        |z <= eq(_T_1, asUInt(y))
+        |""".stripMargin
+    )
+    result should containLine("assign z = x == y;")
+  }
+
+  it should "drop asAsyncReset casts on UInts" in {
+    val compiler = new VerilogCompiler
+    val result = compileBody(
+      """input x : UInt<1>
+        |input y : UInt<1>
+        |output z : AsyncReset
+        |node _T_1 = eq(x, y)
+        |z <= asAsyncReset(_T_1)
+        |""".stripMargin
+    )
+    result should containLine("assign z = x == y;")
+  }
+
 }
 
 class VerilogDescriptionEmitterSpec extends FirrtlFlatSpec {
diff --git a/src/test/scala/firrtlTests/transforms/LegalizeClocks.scala b/src/test/scala/firrtlTests/transforms/LegalizeClocks.scala
new file mode 100644
index 00000000..5c2412ae
--- /dev/null
+++ b/src/test/scala/firrtlTests/transforms/LegalizeClocks.scala
@@ -0,0 +1,67 @@
+// See LICENSE for license details.
+
+package firrtlTests.transforms
+
+import firrtl._
+import firrtlTests.FirrtlFlatSpec
+import firrtlTests.FirrtlCheckers._
+
+class LegalizeClocksTransformSpec extends FirrtlFlatSpec {
+  def compile(input: String): CircuitState =
+    (new MinimumVerilogCompiler).compileAndEmit(CircuitState(parse(input), ChirrtlForm), Nil)
+
+  behavior of "LegalizeClocksTransform"
+
+  it should "not emit @(posedge 1'h0) for stop" in {
+    val input =
+      """circuit test :
+        |  module test :
+        |    stop(asClock(UInt(1)), UInt(1), 1)
+        |""".stripMargin
+    val result = compile(input)
+    result should containLine (s"always @(posedge _GEN_0) begin")
+    result.getEmittedCircuit.value shouldNot include ("always @(posedge 1")
+  }
+
+  it should "not emit @(posedge 1'h0) for printf" in {
+    val input =
+      """circuit test :
+        |  module test :
+        |    printf(asClock(UInt(1)), UInt(1), "hi")
+        |""".stripMargin
+    val result = compile(input)
+    result should containLine (s"always @(posedge _GEN_0) begin")
+    result.getEmittedCircuit.value shouldNot include ("always @(posedge 1")
+  }
+
+  it should "not emit @(posedge 1'h0) for reg" in {
+    val input =
+      """circuit test :
+        |  module test :
+        |    output out : UInt<8>
+        |    input in : UInt<8>
+        |    reg r : UInt<8>, asClock(UInt(0))
+        |    r <= in
+        |    out <= r
+        |""".stripMargin
+    val result = compile(input)
+    result should containLine (s"always @(posedge _GEN_0) begin")
+    result.getEmittedCircuit.value shouldNot include ("always @(posedge 1")
+  }
+
+  it should "deduplicate injected nodes for literal clocks" in {
+    val input =
+      """circuit test :
+        |  module test :
+        |    printf(asClock(UInt(1)), UInt(1), "hi")
+        |    stop(asClock(UInt(1)), UInt(1), 1)
+        |""".stripMargin
+    val result = compile(input)
+    result should containLine (s"wire _GEN_0;")
+    // Check that there's only 1 _GEN_0 instantiation
+    val verilog = result.getEmittedCircuit.value
+    val matches = "wire\\s+_GEN_0;".r.findAllIn(verilog)
+    matches.size should be (1)
+
+  }
+}