Bugfix inferwidth (#372)

* Bugfix: removed recursive removal in infer widths

This will certainly lead to more uninferred width errors, but now widths
that were previously incorrectly inferred are now correctly uninferred.

An example is:
  reg r : UInt, clock with: (reset => (reset, UInt<2>(3)))
  node x = add(r, r)
  r <= x

Here, r's width follows the following formula, which cannot be solved:

rWidth >= max(max(rWidth, rWidth) + 1, 2)

* Added optimizations to for better width inference

Also added exceptions for uninferred widths when checking DoPrim width
legality to not trigger compiler error

* Added additional optimizations

Required for passing all chisel3 tests

1 files changed, 23 insertions, 0 deletions

diff --git a/src/test/scala/firrtlTests/WidthSpec.scala b/src/test/scala/firrtlTests/WidthSpec.scala
index f2938016..9b0ee139 100644
--- a/src/test/scala/firrtlTests/WidthSpec.scala
+++ b/src/test/scala/firrtlTests/WidthSpec.scala
@@ -78,4 +78,27 @@ class WidthSpec extends FirrtlFlatSpec {
       executeTest(input, Nil, passes)
     }
   }
+  "Circular reg depending on reg + 1" should "error" in {
+    val passes = Seq(
+      ToWorkingIR,
+      CheckHighForm,
+      ResolveKinds,
+      InferTypes,
+      CheckTypes,
+      InferWidths,
+      CheckWidths)
+    val input =
+      """circuit Unit :
+        |  module Unit :
+        |    input clock: Clock
+        |    input reset: UInt<1>
+        |    reg r : UInt, clock with :
+        |      reset => (reset, UInt(3))
+        |    node T_7 = add(r, r)
+        |    r <= T_7
+        |""".stripMargin
+    intercept[CheckWidths.UninferredWidth] {
+      executeTest(input, Nil, passes)
+    }
+  }
 }