Revert "Verilog emitter transform InlineNots (#1270)"

This reverts commit f77487d37bd7c61be231a8000a3197d37cf55499.

2 files changed, 0 insertions, 110 deletions

diff --git a/src/test/scala/firrtlTests/ConstantPropagationTests.scala b/src/test/scala/firrtlTests/ConstantPropagationTests.scala
index cc7a5e32..18579ca8 100644
--- a/src/test/scala/firrtlTests/ConstantPropagationTests.scala
+++ b/src/test/scala/firrtlTests/ConstantPropagationTests.scala
@@ -733,78 +733,6 @@ class ConstantPropagationSingleModule extends ConstantPropagationSpec {
     (parse(exec(input))) should be(parse(check))
   }
 
-   "ConstProp" should "propagate boolean equality with true" in {
-    val input =
-      """circuit Top :
-        |  module Top :
-        |    input x : UInt<1>
-        |    output z : UInt<1>
-        |    z <= eq(x, UInt<1>("h1"))
-      """.stripMargin
-    val check =
-      """circuit Top :
-        |  module Top :
-        |    input x : UInt<1>
-        |    output z : UInt<1>
-        |    z <= x
-      """.stripMargin
-    (parse(exec(input))) should be(parse(check))
-  }
-
-   "ConstProp" should "propagate boolean equality with false" in {
-    val input =
-      """circuit Top :
-        |  module Top :
-        |    input x : UInt<1>
-        |    output z : UInt<1>
-        |    z <= eq(x, UInt<1>("h0"))
-      """.stripMargin
-    val check =
-      """circuit Top :
-        |  module Top :
-        |    input x : UInt<1>
-        |    output z : UInt<1>
-        |    z <= not(x)
-      """.stripMargin
-    (parse(exec(input))) should be(parse(check))
-  }
-
-   "ConstProp" should "propagate boolean non-equality with true" in {
-    val input =
-      """circuit Top :
-        |  module Top :
-        |    input x : UInt<1>
-        |    output z : UInt<1>
-        |    z <= neq(x, UInt<1>("h1"))
-      """.stripMargin
-    val check =
-      """circuit Top :
-        |  module Top :
-        |    input x : UInt<1>
-        |    output z : UInt<1>
-        |    z <= not(x)
-      """.stripMargin
-    (parse(exec(input))) should be(parse(check))
-  }
-
-   "ConstProp" should "propagate boolean non-equality with false" in {
-    val input =
-      """circuit Top :
-        |  module Top :
-        |    input x : UInt<1>
-        |    output z : UInt<1>
-        |    z <= neq(x, UInt<1>("h0"))
-      """.stripMargin
-    val check =
-      """circuit Top :
-        |  module Top :
-        |    input x : UInt<1>
-        |    output z : UInt<1>
-        |    z <= x
-      """.stripMargin
-    (parse(exec(input))) should be(parse(check))
-  }
-
   // Optimizing this mux gives: z <= pad(UInt<2>(0), 4)
   // Thus this checks that we then optimize that pad
   "ConstProp" should "optimize nested Expressions" in {
diff --git a/src/test/scala/firrtlTests/VerilogEmitterTests.scala b/src/test/scala/firrtlTests/VerilogEmitterTests.scala
index ad8b8bf9..c5d0eacc 100644
--- a/src/test/scala/firrtlTests/VerilogEmitterTests.scala
+++ b/src/test/scala/firrtlTests/VerilogEmitterTests.scala
@@ -176,44 +176,6 @@ class DoPrimVerilog extends FirrtlFlatSpec {
         |""".stripMargin.split("\n") map normalized
     executeTest(input, check, compiler)
   }
-  "inline Not" should "emit correctly" in {
-    val compiler = new VerilogCompiler
-    val input =
-      """circuit InlineNot :
-        |  module InlineNot :
-        |    input a: UInt<1>
-        |    input b: UInt<1>
-        |    input c: UInt<4>
-        |    output d: UInt<1>
-        |    output e: UInt<1>
-        |    output f: UInt<1>
-        |    output g: UInt<1>
-        |    output h: UInt<1>
-        |    d <= and(a, not(b))
-        |    e <= or(a, not(b))
-        |    f <= not(not(not(bits(c, 2, 2))))
-        |    g <= mux(not(bits(c, 2, 2)), a, b)
-        |    h <= shr(not(bits(c, 2, 1)), 1)""".stripMargin
-    val check =
-      """module InlineNot(
-        |  input   a,
-        |  input   b,
-        |  input  [3:0] c,
-        |  output  d,
-        |  output  e,
-        |  output  f,
-        |  output  g,
-        |  output  h
-        |);
-        |  assign d = a & ~b;
-        |  assign e = a | ~b;
-        |  assign f = ~c[2];
-        |  assign g = c[2] ? b : a;
-        |  assign h = ~c[2];
-        |endmodule
-        |""".stripMargin.split("\n") map normalized
-    executeTest(input, check, compiler)
-  }
   "Rem" should "emit correctly" in {
     val compiler = new VerilogCompiler
     val input =