Merge pull request #626 from freechipsproject/fix-swap-bug

Fix ConstProp bug where multiple names would swap with one

1 files changed, 57 insertions, 0 deletions

diff --git a/src/test/scala/firrtlTests/ConstantPropagationTests.scala b/src/test/scala/firrtlTests/ConstantPropagationTests.scala
index 75c43cf2..e42ecfac 100644
--- a/src/test/scala/firrtlTests/ConstantPropagationTests.scala
+++ b/src/test/scala/firrtlTests/ConstantPropagationTests.scala
@@ -451,6 +451,63 @@ class ConstantPropagationSpec extends FirrtlFlatSpec {
 """
       (parse(exec(input))) should be (parse(check))
    }
+
+   // =============================
+   "ConstProp" should "only swap a given name with one other name" in {
+      val input =
+"""circuit Top :
+  module Top :
+    input x : UInt<1>
+    input y : UInt<1>
+    output z : UInt<3>
+    node _T_1 = add(x, y)
+    node n = _T_1
+    node m = _T_1
+    z <= add(n, m)
+"""
+      val check =
+"""circuit Top :
+  module Top :
+    input x : UInt<1>
+    input y : UInt<1>
+    output z : UInt<3>
+    node n = add(x, y)
+    node _T_1 = n
+    node m = n
+    z <= add(n, n)
+"""
+      (parse(exec(input))) should be (parse(check))
+   }
+
+   "ConstProp" should "NOT swap wire names with node names" in {
+      val input =
+"""circuit Top :
+  module Top :
+    input clock : Clock
+    input x : UInt<1>
+    input y : UInt<1>
+    output z : UInt<1>
+    wire hit : UInt<1>
+    node _T_1 = or(x, y)
+    node _T_2 = eq(_T_1, UInt<1>(1))
+    hit <= _T_2
+    z <= hit
+"""
+      val check =
+"""circuit Top :
+  module Top :
+    input clock : Clock
+    input x : UInt<1>
+    input y : UInt<1>
+    output z : UInt<1>
+    wire hit : UInt<1>
+    node _T_1 = or(x, y)
+    node _T_2 = _T_1
+    hit <= _T_1
+    z <= hit
+"""
+      (parse(exec(input))) should be (parse(check))
+   }
 }
 
 // More sophisticated tests of the full compiler