consolidated wire+assign to just wire, with expression inlined (#1600)

* consolidated wire <type> x; assign x = y; to wire <type> x = y;

* Remove dead code from Emitter.scala

Co-authored-by: Albert Magyar <albert.magyar@gmail.com>

6 files changed, 15 insertions, 20 deletions

diff --git a/src/test/scala/firrtlTests/CompilerTests.scala b/src/test/scala/firrtlTests/CompilerTests.scala
index 1d3e3174..1f793dd2 100644
--- a/src/test/scala/firrtlTests/CompilerTests.scala
+++ b/src/test/scala/firrtlTests/CompilerTests.scala
@@ -176,10 +176,8 @@ class MinimumVerilogCompilerSpec extends CompilerSpec with Matchers {
                  |  input  [2:0] i,
                  |  output [4:0] o
                  |);
-                 |  wire  c;
-                 |  wire  d;
-                 |  assign c = 1'h1;
-                 |  assign d = 1'h1;
+                 |  wire  c = 1'h1;
+                 |  wire  d = 1'h1;
                  |  assign b_0 = 1'h0;
                  |  assign b_1 = c;
                  |  assign b_2 = d;
diff --git a/src/test/scala/firrtlTests/DCETests.scala b/src/test/scala/firrtlTests/DCETests.scala
index f03cd8db..b309467a 100644
--- a/src/test/scala/firrtlTests/DCETests.scala
+++ b/src/test/scala/firrtlTests/DCETests.scala
@@ -502,7 +502,7 @@ class DCECommandLineSpec extends FirrtlFlatSpec {
   "Dead Code Elimination" should "run by default" in {
     firrtl.Driver.execute(args) match {
       case FirrtlExecutionSuccess(_, verilog) =>
-        verilog should not include regex ("wire +a;")
+        verilog should not include regex ("wire +a")
       case _ => fail("Unexpected compilation failure")
     }
   }
@@ -510,7 +510,7 @@ class DCECommandLineSpec extends FirrtlFlatSpec {
   it should "not run when given --no-dce option" in {
     firrtl.Driver.execute(args :+ "--no-dce") match {
       case FirrtlExecutionSuccess(_, verilog) =>
-        verilog should include regex ("wire +a;")
+        verilog should include regex ("wire +a")
       case _ => fail("Unexpected compilation failure")
     }
   }
diff --git a/src/test/scala/firrtlTests/InfoSpec.scala b/src/test/scala/firrtlTests/InfoSpec.scala
index 12ba9151..48567d69 100644
--- a/src/test/scala/firrtlTests/InfoSpec.scala
+++ b/src/test/scala/firrtlTests/InfoSpec.scala
@@ -62,10 +62,9 @@ class InfoSpec extends FirrtlFlatSpec with FirrtlMatchers {
     result should containTree { case DefRegister(Info1, "r", _,_,_,_) => true }
     result should containLine (s"reg [7:0] r; //$Info1")
     result should containTree { case DefNode(Info2, "w", _) => true }
-    result should containLine (s"wire [7:0] w; //$Info2") // Node "w" declaration in Verilog
+    result should containLine (s"wire [7:0] w = x & r; //$Info2") // Node "w" declaration in Verilog
     result should containTree { case DefNode(Info3, "n", _) => true }
-    result should containLine (s"wire [7:0] n; //$Info3")
-    result should containLine (s"assign n = w | x; //$Info3")
+    result should containLine (s"wire [7:0] n = w | x; //$Info3")
   }
 
   it should "be propagated on memories" in {
diff --git a/src/test/scala/firrtlTests/ReplaceTruncatingArithmeticSpec.scala b/src/test/scala/firrtlTests/ReplaceTruncatingArithmeticSpec.scala
index b3c98e88..05a5fe29 100644
--- a/src/test/scala/firrtlTests/ReplaceTruncatingArithmeticSpec.scala
+++ b/src/test/scala/firrtlTests/ReplaceTruncatingArithmeticSpec.scala
@@ -53,7 +53,7 @@ class ReplaceTruncatingArithmeticSpec extends FirrtlFlatSpec {
       |node n = sub(x, y)
       |z <= tail(n, 2)""".stripMargin
     )
-    result should containLine (s"assign n = x - y;")
+    result should containLine (s"wire [8:0] n = x - y;")
     result should containLine (s"assign z = n[6:0];")
   }
 
diff --git a/src/test/scala/firrtlTests/VerilogEmitterTests.scala b/src/test/scala/firrtlTests/VerilogEmitterTests.scala
index 60ab983b..db1b6236 100644
--- a/src/test/scala/firrtlTests/VerilogEmitterTests.scala
+++ b/src/test/scala/firrtlTests/VerilogEmitterTests.scala
@@ -196,9 +196,8 @@ class DoPrimVerilog extends FirrtlFlatSpec {
         |  input  [7:0] in,
         |  output  out
         |);
-        |  wire [7:0] _GEN_0;
+        |  wire [7:0] _GEN_0 = in % 8'h1;
         |  assign out = _GEN_0[0];
-        |  assign _GEN_0 = in % 8'h1;
         |endmodule
         |""".stripMargin.split("\n") map normalized
     executeTest(input, check, compiler)
@@ -223,9 +222,8 @@ class DoPrimVerilog extends FirrtlFlatSpec {
         |  input  [3:0] in4,
         |  output [9:0] out
         |);
-        |  wire [5:0] _GEN_1;
+        |  wire [5:0] _GEN_1 = {in3,in2,in1};
         |  assign out = {in4,_GEN_1};
-        |  assign _GEN_1 = {in3,in2,in1};
         |endmodule
         |""".stripMargin.split("\n") map normalized
 
@@ -714,7 +712,7 @@ class VerilogEmitterSpec extends FirrtlFlatSpec {
         |""".stripMargin
     )
     result shouldNot containLine("assign z = $signed(x) + -2'sh2;")
-    result should    containLine("assign _GEN_0 = $signed(x) - 3'sh2;")
+    result should    containLine("wire [2:0] _GEN_0 = $signed(x) - 3'sh2;")
     result should    containLine("assign z = _GEN_0[1:0];")
   }
 }
@@ -773,13 +771,13 @@ class VerilogDescriptionEmitterSpec extends FirrtlFlatSpec {
       """  /* multi
         |   * line
         |   */
-        |  wire  d;""".stripMargin,
+        |  wire  d = """.stripMargin,
       """  /* multi
         |   * line
         |   */
         |  reg  e;""".stripMargin,
       """  // single line
-        |  wire  f;""".stripMargin
+        |  wire  f = """.stripMargin
     )
     // We don't use executeTest because we care about the spacing in the result
     val modName = ModuleName("Test", CircuitName("Test"))
@@ -858,7 +856,7 @@ class VerilogDescriptionEmitterSpec extends FirrtlFlatSpec {
         |   *
         |   * line6
         |   */
-        |  wire  d;""".stripMargin
+        |  wire  d = """.stripMargin
     )
     // We don't use executeTest because we care about the spacing in the result
     val modName = ModuleName("Test", CircuitName("Test"))
diff --git a/src/test/scala/firrtlTests/transforms/LegalizeClocks.scala b/src/test/scala/firrtlTests/transforms/LegalizeClocks.scala
index d7c76167..f57586f6 100644
--- a/src/test/scala/firrtlTests/transforms/LegalizeClocks.scala
+++ b/src/test/scala/firrtlTests/transforms/LegalizeClocks.scala
@@ -57,10 +57,10 @@ class LegalizeClocksTransformSpec extends FirrtlFlatSpec {
         |    stop(asClock(UInt(1)), UInt(1), 1)
         |""".stripMargin
     val result = compile(input)
-    result should containLine (s"wire _GEN_0;")
+    result should containLine (s"wire  _GEN_0 = 1'h1;")
     // Check that there's only 1 _GEN_0 instantiation
     val verilog = result.getEmittedCircuit.value
-    val matches = "wire\\s+_GEN_0;".r.findAllIn(verilog)
+    val matches = "wire\\s+_GEN_0\\s+=\\s+1'h1".r.findAllIn(verilog)
     matches.size should be (1)
 
   }