Fix Verilog emission for Modelsim compliation

Statements like:

    if (foo)
      x <= y;
    end else begin
      ;
    end

are now emitted without the else clause:

    if (foo)
      x <= y;
    end

and statements like:

    if (foo)
      ;
    end else begin
      x <= y;
    end

are now emitted without the empty statement:

    if (foo)
    end else begin
      x <= y;
    end

0 files changed, 0 insertions, 0 deletions