Merge pull request #1534 from freechipsproject/deprecate-transform-2

Trait-base Dependency API Migration

9 files changed, 91 insertions, 79 deletions

diff --git a/src/test/scala/firrtl/testutils/PassTests.scala b/src/test/scala/firrtl/testutils/PassTests.scala
index 3d820003..7d1b80ac 100644
--- a/src/test/scala/firrtl/testutils/PassTests.scala
+++ b/src/test/scala/firrtl/testutils/PassTests.scala
@@ -4,8 +4,9 @@ package firrtl.testutils
 
 import org.scalatest.flatspec.AnyFlatSpec
 import firrtl.ir.Circuit
+import firrtl.options.{Dependency, IdentityLike}
 import firrtl.passes.{PassExceptions, RemoveEmpty}
-import firrtl.transforms.DedupModules
+import firrtl.stage.Forms
 import firrtl._
 import firrtl.annotations._
 import logger._
@@ -58,49 +59,45 @@ abstract class SimpleTransformSpec extends AnyFlatSpec with FirrtlMatchers with
    }
 }
 
+@deprecated(
+  "Use a TransformManager including 'ReRunResolveAndCheck' as a target. This will be removed in 1.4.",
+  "FIRRTL 1.3"
+)
 class CustomResolveAndCheck(form: CircuitForm) extends SeqTransform {
   def inputForm = form
   def outputForm = form
   def transforms: Seq[Transform] = Seq[Transform](new ResolveAndCheck)
 }
 
+/** Transform that re-runs resolve and check transforms as late as possible, but before any emitters. */
+object ReRunResolveAndCheck extends Transform with DependencyAPIMigration with IdentityLike[CircuitState] {
+
+  override val optionalPrerequisites = Forms.LowFormOptimized
+  override val dependents = Forms.ChirrtlEmitters
+
+  override def invalidates(a: Transform) = {
+    val resolveAndCheck = Forms.Resolved.toSet -- Forms.WorkingIR
+    resolveAndCheck.contains(Dependency.fromTransform(a))
+  }
+
+  override def execute(a: CircuitState) = transform(a)
+
+}
+
 trait LowTransformSpec extends SimpleTransformSpec {
    def emitter = new LowFirrtlEmitter
    def transform: Transform
-   def transforms: Seq[Transform] = Seq(
-      new ChirrtlToHighFirrtl(),
-      new IRToWorkingIR(),
-      new ResolveAndCheck(),
-      new DedupModules(),
-      new HighFirrtlToMiddleFirrtl(),
-      new MiddleFirrtlToLowFirrtl(),
-      new CustomResolveAndCheck(LowForm),
-      transform
-   )
+   def transforms: Seq[Transform] = transform +: ReRunResolveAndCheck +: Forms.LowForm.map(_.getObject)
 }
 
 trait MiddleTransformSpec extends SimpleTransformSpec {
    def emitter = new MiddleFirrtlEmitter
    def transform: Transform
-   def transforms: Seq[Transform] = Seq(
-      new ChirrtlToHighFirrtl(),
-      new IRToWorkingIR(),
-      new ResolveAndCheck(),
-      new DedupModules(),
-      new HighFirrtlToMiddleFirrtl(),
-      new CustomResolveAndCheck(MidForm),
-      transform
-   )
+   def transforms: Seq[Transform] = transform +: ReRunResolveAndCheck +: Forms.MidForm.map(_.getObject)
 }
 
 trait HighTransformSpec extends SimpleTransformSpec {
    def emitter = new HighFirrtlEmitter
    def transform: Transform
-   def transforms = Seq(
-      new ChirrtlToHighFirrtl(),
-      new IRToWorkingIR(),
-      new CustomResolveAndCheck(HighForm),
-      new DedupModules(),
-      transform
-   )
+   def transforms = transform +: ReRunResolveAndCheck +: Forms.HighForm.map(_.getObject)
 }
diff --git a/src/test/scala/firrtlTests/AnnotationTests.scala b/src/test/scala/firrtlTests/AnnotationTests.scala
index 31ee9680..a898d216 100644
--- a/src/test/scala/firrtlTests/AnnotationTests.scala
+++ b/src/test/scala/firrtlTests/AnnotationTests.scala
@@ -35,9 +35,21 @@ trait AnnotationSpec extends LowTransformSpec {
   }
 }
 
+object AnnotationTests {
+
+  class DeletingTransform extends Transform {
+    val inputForm = LowForm
+    val outputForm = LowForm
+    def execute(state: CircuitState) = state.copy(annotations = Seq())
+  }
+
+}
+
 // Abstract but with lots of tests defined so that we can use the same tests
 // for Legacy and newer Annotations
 abstract class AnnotationTests extends AnnotationSpec with Matchers {
+  import AnnotationTests._
+
   def anno(s: String, value: String ="this is a value", mod: String = "Top"): Annotation
   def manno(mod: String): Annotation
 
@@ -59,11 +71,6 @@ abstract class AnnotationTests extends AnnotationSpec with Matchers {
         |  module Top :
         |    input in: UInt<3>
         |""".stripMargin
-    class DeletingTransform extends Transform {
-      val inputForm = LowForm
-      val outputForm = LowForm
-      def execute(state: CircuitState) = state.copy(annotations = Seq())
-    }
     val transform = new DeletingTransform
     val tname = transform.name
     val inlineAnn = InlineAnnotation(CircuitName("Top"))
diff --git a/src/test/scala/firrtlTests/ConstantPropagationTests.scala b/src/test/scala/firrtlTests/ConstantPropagationTests.scala
index bb7fde41..ba952c50 100644
--- a/src/test/scala/firrtlTests/ConstantPropagationTests.scala
+++ b/src/test/scala/firrtlTests/ConstantPropagationTests.scala
@@ -9,7 +9,7 @@ import firrtl.testutils._
 import firrtl.annotations.Annotation
 
 class ConstantPropagationSpec extends FirrtlFlatSpec {
-  val transforms = Seq(
+  val transforms: Seq[Transform] = Seq(
       ToWorkingIR,
       ResolveKinds,
       InferTypes,
diff --git a/src/test/scala/firrtlTests/DCETests.scala b/src/test/scala/firrtlTests/DCETests.scala
index 93934c93..f03cd8db 100644
--- a/src/test/scala/firrtlTests/DCETests.scala
+++ b/src/test/scala/firrtlTests/DCETests.scala
@@ -24,7 +24,7 @@ class DCETests extends FirrtlFlatSpec {
   // deleted
   private val customTransforms = Seq(
     new LowFirrtlOptimization,
-    new SimpleTransform(RemoveEmpty, LowForm)
+    RemoveEmpty
   )
   private def exec(input: String, check: String, annos: Seq[Annotation] = List.empty): Unit = {
     val state = CircuitState(parse(input), ChirrtlForm, annos)
diff --git a/src/test/scala/firrtlTests/InferReadWriteSpec.scala b/src/test/scala/firrtlTests/InferReadWriteSpec.scala
index 9913a7c1..4268bd2b 100644
--- a/src/test/scala/firrtlTests/InferReadWriteSpec.scala
+++ b/src/test/scala/firrtlTests/InferReadWriteSpec.scala
@@ -4,7 +4,9 @@ package firrtlTests
 
 import firrtl._
 import firrtl.ir._
+import firrtl.options.PreservesAll
 import firrtl.passes._
+import firrtl.stage.Forms
 import firrtl.testutils._
 import firrtl.testutils.FirrtlCheckers._
 
@@ -12,9 +14,11 @@ class InferReadWriteSpec extends SimpleTransformSpec {
   class InferReadWriteCheckException extends PassException(
     "Readwrite ports are not found!")
 
-  object InferReadWriteCheck extends Pass {
-    override def inputForm = MidForm
-    override def outputForm = MidForm
+  object InferReadWriteCheck extends Pass with PreservesAll[Transform] {
+    override def prerequisites = Forms.MidForm
+    override def optionalPrerequisites = Seq.empty
+    override def dependents = Forms.MidEmitters
+
     def findReadWrite(s: Statement): Boolean = s match {
       case s: DefMemory if s.readLatency > 0 && s.readwriters.size == 1 =>
         s.name == "mem" && s.readwriters.head == "rw"
diff --git a/src/test/scala/firrtlTests/annotationTests/EliminateTargetPathsSpec.scala b/src/test/scala/firrtlTests/annotationTests/EliminateTargetPathsSpec.scala
index ba8f1698..d4502edb 100644
--- a/src/test/scala/firrtlTests/annotationTests/EliminateTargetPathsSpec.scala
+++ b/src/test/scala/firrtlTests/annotationTests/EliminateTargetPathsSpec.scala
@@ -9,7 +9,25 @@ import firrtl.annotations.transforms.NoSuchTargetException
 import firrtl.transforms.DontTouchAnnotation
 import firrtl.testutils.{FirrtlMatchers, FirrtlPropSpec}
 
+object EliminateTargetPathsSpec {
+
+  case class DummyAnnotation(target: Target) extends SingleTargetAnnotation[Target] {
+    override def duplicate(n: Target): Annotation = DummyAnnotation(n)
+  }
+  class DummyTransform() extends Transform with ResolvedAnnotationPaths {
+    override def inputForm: CircuitForm = LowForm
+    override def outputForm: CircuitForm = LowForm
+
+    override val annotationClasses: Traversable[Class[_]] = Seq(classOf[DummyAnnotation])
+
+    override def execute(state: CircuitState): CircuitState = state
+  }
+
+}
+
 class EliminateTargetPathsSpec extends FirrtlPropSpec with FirrtlMatchers {
+  import EliminateTargetPathsSpec._
+
   val input =
     """circuit Top:
       |  module Leaf:
@@ -48,17 +66,6 @@ class EliminateTargetPathsSpec extends FirrtlPropSpec with FirrtlMatchers {
   val Middle_l2_a = Middle.instOf("l2", "Leaf").ref("a")
   val Leaf_a = Leaf.ref("a")
 
-  case class DummyAnnotation(target: Target) extends SingleTargetAnnotation[Target] {
-    override def duplicate(n: Target): Annotation = DummyAnnotation(n)
-  }
-  class DummyTransform() extends Transform with ResolvedAnnotationPaths {
-    override def inputForm: CircuitForm = LowForm
-    override def outputForm: CircuitForm = LowForm
-
-    override val annotationClasses: Traversable[Class[_]] = Seq(classOf[DummyAnnotation])
-
-    override def execute(state: CircuitState): CircuitState = state
-  }
   val customTransforms = Seq(new DummyTransform())
 
   val inputState = CircuitState(parse(input), ChirrtlForm)
diff --git a/src/test/scala/firrtlTests/options/PhaseManagerSpec.scala b/src/test/scala/firrtlTests/options/PhaseManagerSpec.scala
index f9e4b444..e6504737 100644
--- a/src/test/scala/firrtlTests/options/PhaseManagerSpec.scala
+++ b/src/test/scala/firrtlTests/options/PhaseManagerSpec.scala
@@ -180,7 +180,7 @@ object DependentsFixture {
   }
 
   class Second extends IdentityPhase {
-    override val prerequisites = Seq(Dependency[First])
+    override def prerequisites = Seq(Dependency[First])
     override def invalidates(phase: Phase): Boolean = false
   }
 
@@ -189,8 +189,8 @@ object DependentsFixture {
    * loop detection.
    */
   class Custom extends IdentityPhase {
-    override val prerequisites = Seq(Dependency[First])
-    override val dependents = Seq(Dependency[Second])
+    override def prerequisites = Seq(Dependency[First])
+    override def dependents = Seq(Dependency[Second])
     override def invalidates(phase: Phase): Boolean = false
   }
 
@@ -220,7 +220,7 @@ object ChainedInvalidationFixture {
     override def invalidates(phase: Phase): Boolean = false
   }
   class E extends IdentityPhase {
-    override val prerequisites = Seq(Dependency[A], Dependency[B], Dependency[C], Dependency[D])
+    override def prerequisites = Seq(Dependency[A], Dependency[B], Dependency[C], Dependency[D])
     override def invalidates(phase: Phase): Boolean = false
   }
 
@@ -254,8 +254,8 @@ object UnrelatedFixture {
   class B15 extends IdentityPhase with PreservesAll[Phase]
 
   class B6Sub extends B6 {
-    override val prerequisites = Seq(Dependency[B6])
-    override val dependents = Seq(Dependency[B7])
+    override def prerequisites = Seq(Dependency[B6])
+    override def dependents = Seq(Dependency[B7])
   }
 
   class B6_0 extends B6Sub
@@ -276,7 +276,7 @@ object UnrelatedFixture {
   class B6_15 extends B6Sub
 
   class B8Dep extends B8 {
-    override val dependents = Seq(Dependency[B8])
+    override def dependents = Seq(Dependency[B8])
   }
 
   class B8_0 extends B8Dep
@@ -303,28 +303,28 @@ object CustomAfterOptimizationFixture {
   class Root extends IdentityPhase with PreservesAll[Phase]
 
   class OptMinimum extends IdentityPhase with PreservesAll[Phase] {
-    override val prerequisites = Seq(Dependency[Root])
-    override val dependents = Seq(Dependency[AfterOpt])
+    override def prerequisites = Seq(Dependency[Root])
+    override def dependents = Seq(Dependency[AfterOpt])
   }
 
   class OptFull extends IdentityPhase with PreservesAll[Phase] {
-    override val prerequisites = Seq(Dependency[Root], Dependency[OptMinimum])
-    override val dependents = Seq(Dependency[AfterOpt])
+    override def prerequisites = Seq(Dependency[Root], Dependency[OptMinimum])
+    override def dependents = Seq(Dependency[AfterOpt])
   }
 
   class AfterOpt extends IdentityPhase with PreservesAll[Phase]
 
   class DoneMinimum extends IdentityPhase with PreservesAll[Phase] {
-    override val prerequisites = Seq(Dependency[OptMinimum])
+    override def prerequisites = Seq(Dependency[OptMinimum])
   }
 
   class DoneFull extends IdentityPhase with PreservesAll[Phase] {
-    override val prerequisites = Seq(Dependency[OptFull])
+    override def prerequisites = Seq(Dependency[OptFull])
   }
 
   class Custom extends IdentityPhase with PreservesAll[Phase] {
-    override val prerequisites = Seq(Dependency[Root], Dependency[AfterOpt])
-    override val dependents = Seq(Dependency[DoneMinimum], Dependency[DoneFull])
+    override def prerequisites = Seq(Dependency[Root], Dependency[AfterOpt])
+    override def dependents = Seq(Dependency[DoneMinimum], Dependency[DoneFull])
   }
 
 }
@@ -334,25 +334,25 @@ object OptionalPrerequisitesFixture {
   class Root extends IdentityPhase
 
   class OptMinimum extends IdentityPhase with PreservesAll[Phase] {
-    override val prerequisites = Seq(Dependency[Root])
+    override def prerequisites = Seq(Dependency[Root])
   }
 
   class OptFull extends IdentityPhase with PreservesAll[Phase] {
-    override val prerequisites = Seq(Dependency[Root], Dependency[OptMinimum])
+    override def prerequisites = Seq(Dependency[Root], Dependency[OptMinimum])
   }
 
   class DoneMinimum extends IdentityPhase with PreservesAll[Phase] {
-    override val prerequisites = Seq(Dependency[OptMinimum])
+    override def prerequisites = Seq(Dependency[OptMinimum])
   }
 
   class DoneFull extends IdentityPhase with PreservesAll[Phase] {
-    override val prerequisites = Seq(Dependency[OptFull])
+    override def prerequisites = Seq(Dependency[OptFull])
   }
 
   class Custom extends IdentityPhase with PreservesAll[Phase] {
-    override val prerequisites = Seq(Dependency[Root])
-    override val optionalPrerequisites = Seq(Dependency[OptMinimum], Dependency[OptFull])
-    override val dependents = Seq(Dependency[DoneMinimum], Dependency[DoneFull])
+    override def prerequisites = Seq(Dependency[Root])
+    override def optionalPrerequisites = Seq(Dependency[OptMinimum], Dependency[OptFull])
+    override def dependents = Seq(Dependency[DoneMinimum], Dependency[DoneFull])
   }
 
 }
@@ -369,7 +369,7 @@ object OrderingFixture {
   }
 
   class C extends IdentityPhase {
-    override val prerequisites = Seq(Dependency[A], Dependency[B])
+    override def prerequisites = Seq(Dependency[A], Dependency[B])
     override def invalidates(phase: Phase): Boolean = phase match {
       case _: B => true
       case _    => false
@@ -377,7 +377,7 @@ object OrderingFixture {
   }
 
   class Cx extends C {
-    override val prerequisites = Seq(Dependency[B], Dependency[A])
+    override def prerequisites = Seq(Dependency[B], Dependency[A])
   }
 
 }
diff --git a/src/test/scala/firrtlTests/stage/phases/CompilerSpec.scala b/src/test/scala/firrtlTests/stage/phases/CompilerSpec.scala
index 0582cb21..30574536 100644
--- a/src/test/scala/firrtlTests/stage/phases/CompilerSpec.scala
+++ b/src/test/scala/firrtlTests/stage/phases/CompilerSpec.scala
@@ -27,7 +27,6 @@ class CompilerSpec extends AnyFlatSpec with Matchers {
     s"""|circuit $main:
         |  module $main:
         |    output foo: {bar: UInt}
-        |
         |    foo.bar <= UInt<4>("h0")
         |""".stripMargin
 
@@ -41,9 +40,7 @@ class CompilerSpec extends AnyFlatSpec with Matchers {
       FirrtlCircuitAnnotation(circuitIn),
       CompilerAnnotation(compiler) )
 
-    val expected = Seq(FirrtlCircuitAnnotation(circuitOut))
-
-    phase.transform(input).collect{ case a: FirrtlCircuitAnnotation => a }.toSeq should be (expected)
+    phase.transform(input).toSeq should be (Seq(FirrtlCircuitAnnotation(circuitOut)))
   }
 
   it should "compile multiple FirrtlCircuitAnnotations" in new Fixture {
diff --git a/src/test/scala/firrtlTests/transforms/GroupComponentsSpec.scala b/src/test/scala/firrtlTests/transforms/GroupComponentsSpec.scala
index c280f134..4d38340f 100644
--- a/src/test/scala/firrtlTests/transforms/GroupComponentsSpec.scala
+++ b/src/test/scala/firrtlTests/transforms/GroupComponentsSpec.scala
@@ -362,9 +362,9 @@ class GroupComponentsSpec extends MiddleTransformSpec {
          |    out <= add(in, wrapper.other_out)
          |  module Wrapper :
          |    output other_out: UInt<16>
-         |    inst other of Other
-         |    other_out <= other.out
-         |    other.in is invalid
+         |    inst other_ of Other
+         |    other_out <= other_.out
+         |    other_.in is invalid
          |  module Other:
          |    input in: UInt<16>
          |    output out: UInt<16>