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authorJim Lawson2019-01-08 07:26:20 -0800
committerAdam Izraelevitz2019-01-08 09:26:20 -0600
commit5f0e893c9213464507418a532ee61347a5da26c8 (patch)
tree5bb26fcb4f18387573524d817524fbefb844b1d7 /src/test
parent37567cc65d531b5d47d13c12e9c7ac80fc4d7b1f (diff)
Avoid enforcing time constrains during coverage tests. (#989)
This fixes issue #988 I tried one alternative to this fix: record the time to do a *no rename* run (`depth = 0`) and check that the time to do the *deep rename* (`depth = 500`) was a reasonable multiple of the *no rename* test. Unfortunately, the discrepancies were all over the map, sometime as much three orders of magnitude difference. I decided the current fix was the simplest - don't enforce timing checks if we're doing coverage testing, although determining the latter is brittle.
Diffstat (limited to 'src/test')
-rw-r--r--src/test/scala/firrtlTests/UniquifySpec.scala13
1 files changed, 11 insertions, 2 deletions
diff --git a/src/test/scala/firrtlTests/UniquifySpec.scala b/src/test/scala/firrtlTests/UniquifySpec.scala
index bf0586f3..561f0a84 100644
--- a/src/test/scala/firrtlTests/UniquifySpec.scala
+++ b/src/test/scala/firrtlTests/UniquifySpec.scala
@@ -12,6 +12,7 @@ import firrtl._
import firrtl.annotations._
import firrtl.annotations.TargetToken._
import firrtl.transforms.DontTouchAnnotation
+import firrtl.util.TestOptions
class UniquifySpec extends FirrtlFlatSpec {
@@ -285,6 +286,12 @@ class UniquifySpec extends FirrtlFlatSpec {
}
it should "quickly rename deep bundles" in {
+ // We use a fixed time to determine if this test passed or failed.
+ // This test would pass under normal conditions, but would fail during coverage tests.
+ // Since executions times vary significantly under coverage testing, we check a global
+ // to see if timing measurements are accurate enough to enforce the timing checks.
+ val maxMs = 8000.0
+
def mkType(i: Int): String = {
if(i == 0) "UInt<8>" else s"{x: ${mkType(i - 1)}}"
}
@@ -299,7 +306,9 @@ class UniquifySpec extends FirrtlFlatSpec {
| out <= in
|""".stripMargin
- val (ms, _) = Utils.time(compileToVerilog(input))
- (ms < 8000) shouldBe true
+ val (renameMs, _) = Utils.time(compileToVerilog(input))
+
+ if (TestOptions.accurateTiming)
+ renameMs shouldBe < (maxMs)
}
}