Merge pull request #406 from ucb-bar/addmiddlefirrtlcompiler

Add support for top-level use of MiddleFirrtlCompiler.

3 files changed, 39 insertions, 0 deletions

diff --git a/src/test/scala/firrtlTests/CompilerTests.scala b/src/test/scala/firrtlTests/CompilerTests.scala
index 2a5311f8..a9fce0c2 100644
--- a/src/test/scala/firrtlTests/CompilerTests.scala
+++ b/src/test/scala/firrtlTests/CompilerTests.scala
@@ -14,6 +14,7 @@ import firrtl.{
   CircuitState,
   Compiler,
   HighFirrtlCompiler,
+  MiddleFirrtlCompiler,
   LowFirrtlCompiler,
   Parser,
   VerilogCompiler
@@ -61,6 +62,42 @@ class HighFirrtlCompilerSpec extends CompilerSpec with Matchers {
 }
 
 /**
+  * An example test for testing the MiddleFirrtlCompiler.
+  *
+  * Given an input Firrtl circuit (expressed as a string),
+  * the compiler is executed. The output of the compiler is
+  * a lowered (to MidForm) version of the input circuit. The output is
+  * string compared to the correct lowered circuit.
+  */
+class MiddleFirrtlCompilerSpec extends CompilerSpec with Matchers {
+   val compiler = new MiddleFirrtlCompiler()
+   val input =
+      """
+circuit Top :
+  module Top :
+    input reset : UInt<1>
+    input a : UInt<1>[2]
+    wire b : UInt
+    b <= a[0]
+    when reset :
+      b <= UInt(0)
+"""
+   // Verify that Vecs are retained, but widths are inferred and whens are expanded.
+   val check = Seq(
+      "circuit Top :",
+      "  module Top :",
+      "    input reset : UInt<1>",
+      "    input a : UInt<1>[2]",
+      "    wire b : UInt<1>",
+      "    node _GEN_0 = mux(reset, UInt<1>(\"h0\"), a[0])",
+      "    b <= _GEN_0\n\n"
+   ).reduce(_ + "\n" + _)
+   "A circuit" should "match exactly to its MidForm state" in {
+      (parse(getOutput)) should be (parse(check))
+   }
+}
+
+/**
  * An example test for testing the LoweringCompiler.
  *
  * Given an input Firrtl circuit (expressed as a string),
diff --git a/src/test/scala/firrtlTests/DriverSpec.scala b/src/test/scala/firrtlTests/DriverSpec.scala
index 26b32baa..9f29b918 100644
--- a/src/test/scala/firrtlTests/DriverSpec.scala
+++ b/src/test/scala/firrtlTests/DriverSpec.scala
@@ -156,6 +156,7 @@ class DriverSpec extends FreeSpec with Matchers with BackendCompilationUtilities
       Seq(
         "low" -> "./Dummy.lo.fir",
         "high" -> "./Dummy.hi.fir",
+        "middle" -> "./Dummy.mid.fir",
         "verilog" -> "./Dummy.v"
       ).foreach { case (compilerName, expectedOutputFileName) =>
         val manager = new ExecutionOptionsManager("test") with HasFirrtlOptions {
diff --git a/src/test/scala/firrtlTests/MultiThreadingSpec.scala b/src/test/scala/firrtlTests/MultiThreadingSpec.scala
index 169aa6b2..1698c462 100644
--- a/src/test/scala/firrtlTests/MultiThreadingSpec.scala
+++ b/src/test/scala/firrtlTests/MultiThreadingSpec.scala
@@ -21,6 +21,7 @@ class MultiThreadingSpec extends FirrtlPropSpec {
     // The parameters we're testing with
     val compilers = Seq(
       new firrtl.HighFirrtlCompiler,
+      new firrtl.MiddleFirrtlCompiler,
       new firrtl.LowFirrtlCompiler,
       new firrtl.VerilogCompiler)
     val inputFilePath = s"/integration/GCDTester.fir" // arbitrary