aboutsummaryrefslogtreecommitdiff
path: root/src/test
diff options
context:
space:
mode:
authorAlbert Magyar2020-08-28 18:09:18 -0700
committerGitHub2020-08-28 18:09:18 -0700
commit505fc53338d61acac391d8b04b8bc99fcc92eb69 (patch)
treec406974cfa2ca5925e14770cae485763a1a30177 /src/test
parent318da49f7cb88ce33dcf1418f8b63c0b236be9a8 (diff)
parent8fa7b99d3dff5f199455fa67e90a7dfa6941b8ff (diff)
Merge pull request #1875 from freechipsproject/fix-inline-bools
Restrict boolean inlining to avoid context-sensitive width bugs
Diffstat (limited to 'src/test')
-rw-r--r--src/test/scala/firrtlTests/InlineBooleanExpressionsSpec.scala11
1 files changed, 11 insertions, 0 deletions
diff --git a/src/test/scala/firrtlTests/InlineBooleanExpressionsSpec.scala b/src/test/scala/firrtlTests/InlineBooleanExpressionsSpec.scala
index 1bf7261f..b074e712 100644
--- a/src/test/scala/firrtlTests/InlineBooleanExpressionsSpec.scala
+++ b/src/test/scala/firrtlTests/InlineBooleanExpressionsSpec.scala
@@ -241,4 +241,15 @@ class InlineBooleanExpressionsSpec extends FirrtlFlatSpec {
| out <= _f""".stripMargin
firrtlEquivalenceTest(input, Seq(new InlineBooleanExpressions))
}
+
+ it should "avoid inlining when it would create context-sensitivity bugs" in {
+ val input =
+ """circuit AddNot:
+ | module AddNot:
+ | input a: UInt<1>
+ | input b: UInt<1>
+ | output o: UInt<2>
+ | o <= add(a, not(b))""".stripMargin
+ firrtlEquivalenceTest(input, Seq(new InlineBooleanExpressions))
+ }
}