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authorAlbert Magyar2018-12-21 10:41:35 -0800
committerGitHub2018-12-21 10:41:35 -0800
commit3433f8f8a82c3b129456e9512dd2cf442a6042f6 (patch)
treeada800a0c1e66a0c54bcf7ce4d1cf82fecdef8a2 /src/test
parent93e1f334de0579f513c3ffa03cb5f06c622b4fa8 (diff)
Enhance CheckCombLoops to support annotated ExtModule paths (#962)
Diffstat (limited to 'src/test')
-rw-r--r--src/test/scala/firrtlTests/CheckCombLoopsSpec.scala86
1 files changed, 86 insertions, 0 deletions
diff --git a/src/test/scala/firrtlTests/CheckCombLoopsSpec.scala b/src/test/scala/firrtlTests/CheckCombLoopsSpec.scala
index 8fc7dda9..98472f14 100644
--- a/src/test/scala/firrtlTests/CheckCombLoopsSpec.scala
+++ b/src/test/scala/firrtlTests/CheckCombLoopsSpec.scala
@@ -165,6 +165,92 @@ class CheckCombLoopsSpec extends SimpleTransformSpec {
}
}
+ "Combinational loop through an annotated ExtModule" should "throw an exception" in {
+ val input = """circuit hasloops :
+ | extmodule blackbox :
+ | input in : UInt<1>
+ | output out : UInt<1>
+ | module hasloops :
+ | input clk : Clock
+ | input a : UInt<1>
+ | input b : UInt<1>
+ | output c : UInt<1>
+ | output d : UInt<1>
+ | wire y : UInt<1>
+ | wire z : UInt<1>
+ | c <= b
+ | inst inner of blackbox
+ | inner.in <= y
+ | z <= inner.out
+ | y <= z
+ | d <= z
+ |""".stripMargin
+
+ val mt = ModuleTarget("hasloops", "blackbox")
+ val annos = AnnotationSeq(Seq(ExtModulePathAnnotation(mt.ref("in"), mt.ref("out"))))
+ val writer = new java.io.StringWriter
+ intercept[CheckCombLoops.CombLoopException] {
+ compile(CircuitState(parse(input), ChirrtlForm, annos), writer)
+ }
+ }
+
+ "Loop-free circuit with ExtModulePathAnnotations" should "not throw an exception" in {
+ val input = """circuit hasnoloops :
+ | extmodule blackbox :
+ | input in1 : UInt<1>
+ | input in2 : UInt<1>
+ | output out1 : UInt<1>
+ | output out2 : UInt<1>
+ | module hasnoloops :
+ | input clk : Clock
+ | input a : UInt<1>
+ | output b : UInt<1>
+ | wire x : UInt<1>
+ | inst inner of blackbox
+ | inner.in1 <= a
+ | x <= inner.out1
+ | inner.in2 <= x
+ | b <= inner.out2
+ |""".stripMargin
+
+ val mt = ModuleTarget("hasnoloops", "blackbox")
+ val annos = AnnotationSeq(Seq(
+ ExtModulePathAnnotation(mt.ref("in1"), mt.ref("out1")),
+ ExtModulePathAnnotation(mt.ref("in2"), mt.ref("out2"))))
+ val writer = new java.io.StringWriter
+ compile(CircuitState(parse(input), ChirrtlForm, annos), writer)
+ }
+
+ "Combinational loop through an output RHS reference" should "throw an exception" in {
+ val input = """circuit hasloops :
+ | module thru :
+ | input in : UInt<1>
+ | output tmp : UInt<1>
+ | output out : UInt<1>
+ | tmp <= in
+ | out <= tmp
+ | module hasloops :
+ | input clk : Clock
+ | input a : UInt<1>
+ | input b : UInt<1>
+ | output c : UInt<1>
+ | output d : UInt<1>
+ | wire y : UInt<1>
+ | wire z : UInt<1>
+ | c <= b
+ | inst inner of thru
+ | inner.in <= y
+ | z <= inner.out
+ | y <= z
+ | d <= z
+ |""".stripMargin
+
+ val writer = new java.io.StringWriter
+ intercept[CheckCombLoops.CombLoopException] {
+ compile(CircuitState(parse(input), ChirrtlForm), writer)
+ }
+ }
+
"Multiple simple loops in one SCC" should "throw an exception" in {
val input = """circuit hasloops :
| module hasloops :