diff options
| author | Schuyler Eldridge | 2020-02-13 11:28:12 -0500 |
|---|---|---|
| committer | Schuyler Eldridge | 2020-03-02 10:27:04 -0500 |
| commit | 2ec6022e3c02b1b7f452d89de61790e005099ca2 (patch) | |
| tree | 1e3a68dfb374e494859659951961a35ea4fb708b /src/test | |
| parent | d44d3f8f1a15f2b15ba338a733ff87a83ecba1ac (diff) | |
Remove new unreachables in EliminateTargetPaths
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Diffstat (limited to 'src/test')
| -rw-r--r-- | src/test/scala/firrtlTests/annotationTests/EliminateTargetPathsSpec.scala | 26 |
1 files changed, 24 insertions, 2 deletions
diff --git a/src/test/scala/firrtlTests/annotationTests/EliminateTargetPathsSpec.scala b/src/test/scala/firrtlTests/annotationTests/EliminateTargetPathsSpec.scala index 9d7df718..11c40d5f 100644 --- a/src/test/scala/firrtlTests/annotationTests/EliminateTargetPathsSpec.scala +++ b/src/test/scala/firrtlTests/annotationTests/EliminateTargetPathsSpec.scala @@ -380,7 +380,8 @@ class EliminateTargetPathsSpec extends FirrtlPropSpec with FirrtlMatchers { | node x = UInt<1>(0) | skip | module Foo: - | inst bar of Bar""".stripMargin + | inst bar of Bar + | inst baz of Bar""".stripMargin val Bar_x = CircuitTarget("Foo").module("Bar").ref("x") val output = CircuitState(passes.ToWorkingIR.run(Parser.parse(input)), UnknownForm, Seq(DontTouchAnnotation(Bar_x))) .resolvePaths(Seq(CircuitTarget("Foo").module("Foo").instOf("bar", "Bar"))) @@ -394,6 +395,27 @@ class EliminateTargetPathsSpec extends FirrtlPropSpec with FirrtlMatchers { .filter{ case _: DeletedAnnotation => false case _ => true - } should contain (DontTouchAnnotation(newBar_x)) + } should contain allOf (DontTouchAnnotation(newBar_x), DontTouchAnnotation(Bar_x)) + } + + property("It should not rename lone instances") { + val input = + """|circuit Foo: + | module Baz: + | skip + | module Bar: + | inst baz of Baz + | skip + | module Foo: + | inst bar of Bar + |""".stripMargin + val targets = Seq( + CircuitTarget("Foo").module("Foo").instOf("bar", "Bar").instOf("baz", "Baz") + ) + val output = CircuitState(passes.ToWorkingIR.run(Parser.parse(input)), UnknownForm, Nil) + .resolvePaths(targets) + + info(output.circuit.serialize) + } } |
