Fix dynamic SubAccess of zero-length vectors (#1450)

* Fix dynamic SubAccess of zero-length vectors

* Fixes #230
* Add new ZeroLengthVecs pass that occurs before RemoveAccesses
* Include this in stage.Forms.MidForm
* Add to High->Mid order in compiler test based on @seldridge feedback

* Use validif to produce out-of-bounds value in ZeroLengthVecs

* Update scaladoc

* Fix test imports

2 files changed, 75 insertions, 6 deletions

diff --git a/src/test/scala/firrtlTests/LoweringCompilersSpec.scala b/src/test/scala/firrtlTests/LoweringCompilersSpec.scala
index dcc4e48d..648e45cd 100644
--- a/src/test/scala/firrtlTests/LoweringCompilersSpec.scala
+++ b/src/test/scala/firrtlTests/LoweringCompilersSpec.scala
@@ -61,6 +61,7 @@ class LoweringCompilersSpec extends FlatSpec with Matchers {
       passes.PullMuxes,
       passes.ReplaceAccesses,
       passes.ExpandConnects,
+      passes.ZeroLengthVecs,
       passes.RemoveAccesses,
       passes.Uniquify,
       passes.ExpandWhens,
@@ -156,17 +157,17 @@ class LoweringCompilersSpec extends FlatSpec with Matchers {
   it should "replicate the old order" in {
     val tm = new TransformManager(Forms.MidForm, Forms.Deduped)
     val patches = Seq(
-      Add(5, Seq(Dependency(firrtl.passes.ResolveKinds),
+      Add(6, Seq(Dependency(firrtl.passes.ResolveKinds),
                  Dependency(firrtl.passes.InferTypes))),
-      Del(6),
       Del(7),
-      Add(6, Seq(Dependency[firrtl.passes.ExpandWhensAndCheck])),
-      Del(10),
+      Del(8),
+      Add(7, Seq(Dependency[firrtl.passes.ExpandWhensAndCheck])),
       Del(11),
       Del(12),
-      Add(11, Seq(Dependency(firrtl.passes.ResolveFlows),
+      Del(13),
+      Add(12, Seq(Dependency(firrtl.passes.ResolveFlows),
                   Dependency[firrtl.passes.InferWidths])),
-      Del(13)
+      Del(14)
     )
     compare(legacyTransforms(new HighFirrtlToMiddleFirrtl), tm, patches)
   }
diff --git a/src/test/scala/firrtlTests/ZeroLengthVecsSpec.scala b/src/test/scala/firrtlTests/ZeroLengthVecsSpec.scala
new file mode 100644
index 00000000..715714dd
--- /dev/null
+++ b/src/test/scala/firrtlTests/ZeroLengthVecsSpec.scala
@@ -0,0 +1,68 @@
+// See LICENSE for license details.
+
+package firrtlTests
+
+import firrtl._
+import firrtl.passes._
+import firrtl.testutils.FirrtlFlatSpec
+
+class ZeroLengthVecsSpec extends FirrtlFlatSpec {
+  val transforms = Seq(
+    ToWorkingIR,
+    ResolveKinds,
+    InferTypes,
+    ResolveFlows,
+    new InferWidths,
+    ZeroLengthVecs,
+    CheckTypes)
+  protected def exec(input: String) = {
+    transforms.foldLeft(CircuitState(parse(input), UnknownForm)) {
+      (c: CircuitState, t: Transform) => t.runTransform(c)
+    }.circuit.serialize
+  }
+
+  "ZeroLengthVecs" should "drop subaccesses to zero-length vectors" in {
+    val input =
+      """circuit bar :
+        |  module bar :
+        |    input i : { a : UInt<8>, b : UInt<4> }[0]
+        |    input sel : UInt<1>
+        |    output foo : UInt<1>[0]
+        |    output o : UInt<8>
+        |    foo[UInt<1>(0)] <= UInt<1>(0)
+        |    o <= i[sel].a
+        |""".stripMargin
+    val check =
+      """circuit bar :
+        |  module bar :
+        |    input i : { a : UInt<8>, b : UInt<4> }[0]
+        |    input sel : UInt<1>
+        |    output foo : UInt<1>[0]
+        |    output o : UInt<8>
+        |    skip
+        |    o <= validif(UInt<1>(0), UInt<8>(0))
+        |""".stripMargin
+    (parse(exec(input))) should be (parse(check))
+  }
+
+  "ZeroLengthVecs" should "handle intervals correctly" in {
+    val input =
+      """circuit bar :
+        |  module bar :
+        |    input i : Interval[3,4].0[0]
+        |    input sel : UInt<1>
+        |    output o : Interval[3,4].0
+        |    o <= i[sel]
+        |""".stripMargin
+    val check =
+      """circuit bar :
+        |  module bar :
+        |    input i : Interval[3,4].0[0]
+        |    input sel : UInt<1>
+        |    output o : Interval[3,4].0
+        |    o <= validif(UInt<1>(0), clip(asInterval(SInt<1>(0), 0, 0, 0), i[sel]))
+        |""".stripMargin
+    (parse(exec(input))) should be (parse(check))
+  }
+
+}