Implement File Info

7 files changed, 13 insertions, 10 deletions

diff --git a/src/test/scala/firrtlTests/CheckInitializationSpec.scala b/src/test/scala/firrtlTests/CheckInitializationSpec.scala
index 58477e07..49d5bc08 100644
--- a/src/test/scala/firrtlTests/CheckInitializationSpec.scala
+++ b/src/test/scala/firrtlTests/CheckInitializationSpec.scala
@@ -31,10 +31,11 @@ import java.io._
 import org.scalatest._
 import org.scalatest.prop._
 import firrtl._
+import firrtl.Parser.IgnoreInfo
 import firrtl.passes._
 
 class CheckInitializationSpec extends FirrtlFlatSpec {
-  private def parse(input: String) = Parser.parse("", input.split("\n").toIterator, false)
+  private def parse(input: String) = Parser.parse(input.split("\n").toIterator, IgnoreInfo)
   private val passes = Seq(
      ToWorkingIR,
      CheckHighForm,
diff --git a/src/test/scala/firrtlTests/CheckSpec.scala b/src/test/scala/firrtlTests/CheckSpec.scala
index 4a646c38..ea0767bb 100644
--- a/src/test/scala/firrtlTests/CheckSpec.scala
+++ b/src/test/scala/firrtlTests/CheckSpec.scala
@@ -20,7 +20,7 @@ class CheckSpec extends FlatSpec with Matchers {
         |      read-latency => 0
         |      write-latency => 1""".stripMargin
     intercept[PassExceptions] {
-      passes.foldLeft(Parser.parse("",input.split("\n").toIterator)) {
+      passes.foldLeft(Parser.parse(input.split("\n").toIterator)) {
         (c: Circuit, p: Pass) => p.run(c)
       }
     }
diff --git a/src/test/scala/firrtlTests/ChirrtlSpec.scala b/src/test/scala/firrtlTests/ChirrtlSpec.scala
index dd2b7e31..0059d7ed 100644
--- a/src/test/scala/firrtlTests/ChirrtlSpec.scala
+++ b/src/test/scala/firrtlTests/ChirrtlSpec.scala
@@ -67,7 +67,7 @@ class ChirrtlSpec extends FirrtlFlatSpec {
        |      infer mport y = ram[UInt(4)], newClock
        |      y <= UInt(5)
        """.stripMargin
-    passes.foldLeft(Parser.parse("",input.split("\n").toIterator)) {
+    passes.foldLeft(Parser.parse(input.split("\n").toIterator)) {
       (c: Circuit, p: Pass) => p.run(c)
     }
   }
diff --git a/src/test/scala/firrtlTests/ConstantPropagationTests.scala b/src/test/scala/firrtlTests/ConstantPropagationTests.scala
index 5f5705d9..cfcb7f45 100644
--- a/src/test/scala/firrtlTests/ConstantPropagationTests.scala
+++ b/src/test/scala/firrtlTests/ConstantPropagationTests.scala
@@ -3,6 +3,7 @@ package firrtlTests
 import org.scalatest.Matchers
 import java.io.{StringWriter,Writer}
 import firrtl._
+import firrtl.Parser.IgnoreInfo
 import firrtl.passes._
 
 // Tests the following cases for constant propagation:
@@ -20,7 +21,7 @@ class ConstantPropagationSpec extends FirrtlFlatSpec {
       ResolveGenders,
       InferWidths,
       ConstProp)
-  def parse(input: String): Circuit = Parser.parse("", input.split("\n").toIterator, false)
+  def parse(input: String): Circuit = Parser.parse(input.split("\n").toIterator, IgnoreInfo)
   private def exec (input: String) = {
     passes.foldLeft(parse(input)) {
       (c: Circuit, p: Pass) => p.run(c)
diff --git a/src/test/scala/firrtlTests/LowerTypesSpec.scala b/src/test/scala/firrtlTests/LowerTypesSpec.scala
index 8da10b3a..736849f5 100644
--- a/src/test/scala/firrtlTests/LowerTypesSpec.scala
+++ b/src/test/scala/firrtlTests/LowerTypesSpec.scala
@@ -32,7 +32,7 @@ class LowerTypesSpec extends FirrtlFlatSpec {
     LowerTypes)
 
   private def executeTest(input: String, expected: Seq[String]) = {
-    val c = passes.foldLeft(Parser.parse("", input.split("\n").toIterator)) {
+    val c = passes.foldLeft(Parser.parse(input.split("\n").toIterator)) {
       (c: Circuit, p: Pass) => p.run(c)
     }
     val lines = c.serialize.split("\n") map normalized
diff --git a/src/test/scala/firrtlTests/UniquifySpec.scala b/src/test/scala/firrtlTests/UniquifySpec.scala
index 7e01c3eb..71f41074 100644
--- a/src/test/scala/firrtlTests/UniquifySpec.scala
+++ b/src/test/scala/firrtlTests/UniquifySpec.scala
@@ -44,7 +44,7 @@ class UniquifySpec extends FirrtlFlatSpec {
   )
 
   private def executeTest(input: String, expected: Seq[String]) = {
-    val c = passes.foldLeft(Parser.parse("", input.split("\n").toIterator)) {
+    val c = passes.foldLeft(Parser.parse(input.split("\n").toIterator)) {
       (c: Circuit, p: Pass) => p.run(c)
     }
     val lines = c.serialize.split("\n") map normalized
diff --git a/src/test/scala/firrtlTests/UnitTests.scala b/src/test/scala/firrtlTests/UnitTests.scala
index 7276aabb..cee2c15d 100644
--- a/src/test/scala/firrtlTests/UnitTests.scala
+++ b/src/test/scala/firrtlTests/UnitTests.scala
@@ -32,11 +32,12 @@ import org.scalatest._
 import org.scalatest.prop._
 import firrtl._
 import firrtl.passes._
+import firrtl.Parser.IgnoreInfo
 
 class UnitTests extends FirrtlFlatSpec {
-  def parse (input:String) = Parser.parse("",input.split("\n").toIterator,false)
+  def parse (input:String) = Parser.parse(input.split("\n").toIterator, IgnoreInfo)
   private def executeTest(input: String, expected: Seq[String], passes: Seq[Pass]) = {
-    val c = passes.foldLeft(Parser.parse("", input.split("\n").toIterator)) {
+    val c = passes.foldLeft(Parser.parse(input.split("\n").toIterator)) {
       (c: Circuit, p: Pass) => p.run(c)
     }
     val lines = c.serialize.split("\n") map normalized
@@ -132,7 +133,7 @@ class UnitTests extends FirrtlFlatSpec {
       ToWorkingIR,
       InferTypes)
     intercept[PassException] {
-      val c = Parser.parse("",splitExpTestCode.split("\n").toIterator)
+      val c = Parser.parse(splitExpTestCode.split("\n").toIterator)
       val c2 = passes.foldLeft(c)((c, p) => p run c)
       new VerilogEmitter().run(c2, new OutputStreamWriter(new ByteArrayOutputStream))
     }
@@ -143,7 +144,7 @@ class UnitTests extends FirrtlFlatSpec {
       ToWorkingIR,
       SplitExpressions,
       InferTypes)
-    val c = Parser.parse("",splitExpTestCode.split("\n").toIterator)
+    val c = Parser.parse(splitExpTestCode.split("\n").toIterator)
     val c2 = passes.foldLeft(c)((c, p) => p run c)
     new VerilogEmitter().run(c2, new OutputStreamWriter(new ByteArrayOutputStream))
   }