diff options
| author | Jack Koenig | 2020-04-14 11:17:38 -0700 |
|---|---|---|
| committer | GitHub | 2020-04-14 11:17:38 -0700 |
| commit | 0407a53bd76b41deed44dffbe08ca252536ab53c (patch) | |
| tree | 86907dad790ba234ea85cc30108af221313f57f6 /src/test | |
| parent | f8546a7c165e0bde4b3e5682dd6edd0a3e199b31 (diff) | |
| parent | 74ff30cf8dcfb7253458905b626dee89fc9b280c (diff) | |
Merge pull request #1525 from freechipsproject/async-self-init-supported
Prevent infinite recursion in CheckResets
Diffstat (limited to 'src/test')
| -rw-r--r-- | src/test/scala/firrtlTests/AsyncResetSpec.scala | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/src/test/scala/firrtlTests/AsyncResetSpec.scala b/src/test/scala/firrtlTests/AsyncResetSpec.scala index 60eab883..34211946 100644 --- a/src/test/scala/firrtlTests/AsyncResetSpec.scala +++ b/src/test/scala/firrtlTests/AsyncResetSpec.scala @@ -117,6 +117,20 @@ class AsyncResetSpec extends FirrtlFlatSpec { } } + "Self-inits" should "NOT cause infinite loops in CheckResets" in { + val result = compileBody(s""" + |input clock : Clock + |input reset : AsyncReset + |input in : UInt<12> + |output out : UInt<10> + | + |reg a : UInt<10>, clock with : + | reset => (reset, a) + |out <= UInt<5>("h15")""".stripMargin + ) + result should containLine("assign out = 10'h15;") + } + "Late non-literals connections" should "NOT be allowed as reset values for AsyncReset" in { an [checks.CheckResets.NonLiteralAsyncResetValueException] shouldBe thrownBy { compileBody(s""" |
