diff options
| author | Jack Koenig | 2020-08-14 19:48:35 -0700 |
|---|---|---|
| committer | Jack Koenig | 2020-08-14 19:48:35 -0700 |
| commit | 9adbe1ede59f9aeb25e71fd8318a4e7e46c4cc34 (patch) | |
| tree | f06060e9fb52f4f5b30bc56db78acb6bd371642d /src/test/scala | |
| parent | 6fc742bfaf5ee508a34189400a1a7dbffe3f1cac (diff) | |
Apply scalafmt again
Diffstat (limited to 'src/test/scala')
| -rw-r--r-- | src/test/scala/firrtlTests/VerilogEmitterTests.scala | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/src/test/scala/firrtlTests/VerilogEmitterTests.scala b/src/test/scala/firrtlTests/VerilogEmitterTests.scala index 9840229e..42f0bf85 100644 --- a/src/test/scala/firrtlTests/VerilogEmitterTests.scala +++ b/src/test/scala/firrtlTests/VerilogEmitterTests.scala @@ -373,10 +373,13 @@ class VerilogEmitterSpec extends FirrtlFlatSpec { val renderer = emitter.getRenderer(module, moduleMap)(writer) - renderer.emitVerilogBind("BindsToTest", """ - |$readmemh("file", memory); - | - |""".stripMargin) + renderer.emitVerilogBind( + "BindsToTest", + """ + |$readmemh("file", memory); + | + |""".stripMargin + ) val lines = writer.toString.split("\n") val outString = writer.toString |