Legalize neg: -x becomes 0 - x (#2128)

This fixes an error with negating a negative SInt literal and a
[debatable] lint warning in Verilator when negating any value.

This behavior matches that of Chisel (which directly emits the 0 - x
already).

2 files changed, 49 insertions, 1 deletions

diff --git a/src/test/scala/firrtlTests/LegalizeSpec.scala b/src/test/scala/firrtlTests/LegalizeSpec.scala
index 905d578e..ad85668e 100644
--- a/src/test/scala/firrtlTests/LegalizeSpec.scala
+++ b/src/test/scala/firrtlTests/LegalizeSpec.scala
@@ -2,6 +2,8 @@
 
 package firrtlTests
 
-import firrtl.testutils.ExecutionTest
+import firrtl.testutils.{ExecutionTest, ExecutionTestNoOpt}
 
 class LegalizeExecutionTest extends ExecutionTest("Legalize", "/passes/Legalize")
+// Legalize also needs to work when optimizations are turned off
+class LegalizeExecutionTestNoOpt extends ExecutionTestNoOpt("Legalize", "/passes/Legalize")
diff --git a/src/test/scala/firrtlTests/NegSpec.scala b/src/test/scala/firrtlTests/NegSpec.scala
new file mode 100644
index 00000000..c60294e3
--- /dev/null
+++ b/src/test/scala/firrtlTests/NegSpec.scala
@@ -0,0 +1,46 @@
+// SPDX-License-Identifier: Apache-2.0
+
+package firrtlTests
+
+import firrtl.testutils._
+
+class NegSpec extends FirrtlFlatSpec {
+  "unsigned neg" should "be correct and lint-clean" in {
+    val input =
+      """|circuit UnsignedNeg :
+         |  module UnsignedNeg  :
+         |    input in : UInt<8>
+         |    output out : SInt
+         |    out <= neg(in)
+         |""".stripMargin
+    val expected =
+      """|module UnsignedNegRef(
+         |  input [7:0] in,
+         |  output [8:0] out
+         |);
+         |  assign out = 8'd0 - in;
+         |endmodule""".stripMargin
+    firrtlEquivalenceWithVerilog(input, expected)
+    lintVerilog(compileToVerilog(input))
+  }
+
+  "signed neg" should "be correct and lint-clean" in {
+    val input =
+      """|circuit SignedNeg :
+         |  module SignedNeg  :
+         |    input in : SInt<8>
+         |    output out : SInt
+         |    out <= neg(in)
+         |""".stripMargin
+    // -$signed(in) is a lint warning in Verilator but is functionally correct
+    val expected =
+      """|module SignedNegRef(
+         |  input [7:0] in,
+         |  output [8:0] out
+         |);
+         |  assign out = -$signed(in);
+         |endmodule""".stripMargin
+    firrtlEquivalenceWithVerilog(input, expected)
+    lintVerilog(compileToVerilog(input))
+  }
+}